公开(公告)号：US10725860B2

公开(公告)日：2020-07-28

申请号：US15968468

申请日：2018-05-01

Applicant: SanDisk Technologies LLC

Inventor： David Avraham ,  Ran Zamir ,  Eran Sharon

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  H03M13/27 ,  G11C29/52 ,  H03M13/17 ,  G06F16/901 ,  H03M13/29

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.

公开(公告)号：US20180287632A1

公开(公告)日：2018-10-04

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  ldan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  ldan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

CPC classification number: H03M13/11 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  H03M13/1125 ,  H03M13/6566

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10236909B2

公开(公告)日：2019-03-19

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10218384B2

公开(公告)日：2019-02-26

申请号：US15366859

申请日：2016-12-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Idan Goldenberg ,  Ishai Ilani ,  Idan Alrod ,  Yuri Ryabinin ,  Yan Dumchin ,  Mark Fiterman ,  Ran Zamir

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/17 ,  H03M13/37

Abstract: A device includes a low density parity check (LDPC) decoder that configured to receive a representation of a codeword. The LDPC decoder includes a message memory configured to store decoding messages, multiple data processing units (DPUs), a control circuit, and a reording circuit. The control circuit is configured to enable a first number of the DPUs to decode the representation of the codeword in response to a decoding mode indicator indicating a first decoding mode and to enable a second number of the DPUs to decode the representation of the codeword in response to the decoding mode indicator indicating a second decoding mode. The reordering circuit is configured to selectively reorder at least one of the decoding messages based on the decoding mode indicator.

公开(公告)号：US10158380B2

公开(公告)日：2018-12-18

申请号：US15371167

申请日：2016-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Alexander Bazarsky ,  Idan Goldenberg ,  Stella Achtenberg ,  Omer Fainzilber ,  Ran Zamir

IPC: G11C29/00 ,  H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

公开(公告)号：US10116333B2

公开(公告)日：2018-10-30

申请号：US15223531

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ran Zamir ,  Alexander Bazarsky ,  Stella Achtenberg ,  Omer Fainzilber ,  Eran Sharon

IPC: H03M13/11 ,  G11C16/08 ,  G06F11/10 ,  H03M13/00 ,  G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

公开(公告)号：US10110249B2

公开(公告)日：2018-10-23

申请号：US15244444

申请日：2016-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xinmiao Zhang ,  Alexander Bazarsky ,  Ran Zamir ,  Eran Sharon ,  Idan Alrod ,  Omer Fainzilber ,  Sanel Alterman

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  G11C29/52

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

公开(公告)号：US10355712B2

公开(公告)日：2019-07-16

申请号：US15475602

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  G06F11/10 ,  G06F3/06 ,  H03M13/00 ,  H03M13/37

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10075190B2

公开(公告)日：2018-09-11

申请号：US14924627

申请日：2015-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Stella Achtenberg ,  Eran Sharon ,  Ran Zamir

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  G11C29/52 ,  H03M13/45 ,  H03M13/11 ,  H03M13/15 ,  H03M13/29

CPC classification number: H03M13/3746 ,  G06F11/10 ,  G06F11/1072 ,  G11C29/52 ,  H03M13/1108 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/1191 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/45

Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.

公开(公告)号：US20180246783A1

公开(公告)日：2018-08-30

申请号：US15968468

申请日：2018-05-01

Applicant: SanDisk Technologies LLC

Inventor： David Avraham ,  Ran Zamir ,  Eran Sharon

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/17 ,  G06F17/30

Abstract: A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.