公开(公告)号：US20210257378A1

公开(公告)日：2021-08-19

申请号：US16794536

申请日：2020-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu UEDA ,  Michiaki SANO

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a composite charge storage structure, a tunneling dielectric layer, and a vertical semiconductor channel. The composite charge storage structure may include a vertical stack of tubular charge storage material portions including a first charge trapping material located at levels of the electrically conductive layers, and a charge storage layer including a second charge trapping material extending through a plurality of electrically conductive layers of the electrically conductive layers. The first charge trapping material has a higher charge trap density than the second charge trapping material. Alternatively, the composite charge storage material portions may include discrete charge storage elements each containing a silicon nitride portion and a silicon carbide nitride liner.

公开(公告)号：US20200020715A1

公开(公告)日：2020-01-16

申请号：US16242245

申请日：2019-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Yu UEDA ,  Tatsuya HINOUE ,  Shigehisa INOUE ,  Genta MIZUNO ,  Masanori TSUTSUMI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

公开(公告)号：US20220216145A1

公开(公告)日：2022-07-07

申请号：US17655827

申请日：2022-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori TSUTSUMI ,  Naohiro HOSODA ,  Shuichi HAMAGUCHI ,  Kazuki ISOZUMI ,  Genta MIZUNO ,  Yusuke MUKAE ,  Ryo NAKAMURA ,  Yu UEDA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.