公开(公告)号：US20230363165A1

公开(公告)日：2023-11-09

申请号：US18347838

申请日：2023-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Kazushi KOMEDA ,  Zhen CHEN

IPC: H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes an alternating stack of insulating layers and composite layers, each of the composite layers includes a plurality of electrically conductive word line strips and a plurality of dielectric isolation structures, and each of the insulating layers has an areal overlap with each electrically conductive word line strip and each dielectric isolation structure within the composite layers within a memory array region in a plan view along a vertical direction, rows of memory openings arranged along the first horizontal direction, where each row of memory openings of the rows of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers, and rows of memory opening fill structures located within the rows of memory openings, where each of the memory opening fill structures includes a vertical stack of memory elements and a vertical semiconductor channel.

公开(公告)号：US20190088717A1

公开(公告)日：2019-03-21

申请号：US15711075

申请日：2017-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chao Feng YEH ,  Jongsun SEL ,  Zhen CHEN

IPC: H01L27/24 ,  H01L45/00

Abstract: Doped semiconductor strips, a planar insulating spacer layer, a gate conductor material layer, and a dielectric cap layer are formed over a substrate. A two-dimensional array of openings is formed through the dielectric cap layer and the gate electrode material layer. Gate dielectrics are formed in the two-dimensional array of openings, and vertical semiconductor channels are formed on each of the gate dielectrics. Gate divider rail structures are formed through the gate conductor material layer. The gate divider rail structures divide the gate conductor material layer into a one-dimensional array of gate electrode lines. Each of the gate electrode lines includes a one-dimensional array of openings arranged along a horizontal direction to form a two-dimensional array of hole-type surrounding gate vertical field effect transistors.

公开(公告)号：US20210143166A1

公开(公告)日：2021-05-13

申请号：US17126504

申请日：2020-12-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhen CHEN ,  Yanli ZHANG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.

公开(公告)号：US20180158873A1

公开(公告)日：2018-06-07

申请号：US15367791

申请日：2016-12-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michiaki SANO ,  Zhen CHEN ,  Tetsuya YAMADA ,  Akira NAKADA ,  Yasuke ODA ,  Manabu HAYASHI ,  Shigenori SATO

IPC: H01L27/24 ,  H01L27/115 ,  H01L45/00

CPC classification number: H01L45/16 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A wedge-shaped contact region can be employed to provide electrical contacts to multiple electrically conductive layers in a three-dimensional device structure. A cavity including a generally wedge-shaped region and a primary region is formed in a dielectric matrix layer over a support structure. An alternating stack of insulating layers and electrically conductive layers is formed by a series of conformal deposition processes in the cavity and over the dielectric matrix layer. The alternating stack can be planarized employing the top surface of the dielectric matrix layer as a stopping layer. A tip portion of each electrically conductive layer within remaining portions of the alternating stack is laterally offset from the tip of the generally wedge-shaped region by a respective lateral offset distance along a lateral protrusion direction. Contact via structures can be formed on the tip portions of the electrically conductive layers to provide electrical contact.