公开(公告)号：US20240055503A1

公开(公告)日：2024-02-15

申请号：US17818880

申请日：2022-08-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Arash ELHAMI KHORASANI ,  Mark GRISWOLD

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L29/7816 ,  H01L29/0692 ,  H01L29/66659

Abstract: In an example, a semiconductor device includes a region of semiconductor material, a first dielectric over the region of semiconductor material, a first gate conductor over a first portion of the first dielectric, and a second gate conductor over a second portion of the first dielectric and laterally spaced apart from the first gate conductor. A first conductor is coupled to the first gate conductor and a second conductor coupled to the second gate conductor and laterally separated from the first conductor by a first spacing. A second dielectric is within the first spacing. The first conductor and the second conductor are laterally capacitively coupled, the first gate conductor is vertically capacitively coupled to the region of semiconductor material, and the second gate conductor is vertically capacitively coupled to the region of semiconductor material.

公开(公告)号：US20220209008A1

公开(公告)日：2022-06-30

申请号：US17139748

申请日：2020-12-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize CHEN ,  Mark GRISWOLD ,  Jaroslav PJENCAK

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

公开(公告)号：US20220262949A1

公开(公告)日：2022-08-18

申请号：US17178729

申请日：2021-02-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize CHEN ,  Mark GRISWOLD

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/761 ,  H01L29/66

Abstract: In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

公开(公告)号：US20200266263A1

公开(公告)日：2020-08-20

申请号：US16447005

申请日：2019-06-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Arash ELHAMI KHORASANI ,  Mark GRISWOLD

IPC: H01L49/02 ,  H01L27/06

Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

公开(公告)号：US20190043856A1

公开(公告)日：2019-02-07

申请号：US15669579

申请日：2017-08-04

Applicant: Semiconductor Components Industries, LLC

Inventor： Moshe AGAM ,  Johan Camiel Julia JANSSENS ,  Jaroslav PJENCAK ,  Thierry YAO ,  Mark GRISWOLD ,  Weize CHEN

IPC: H01L27/07 ,  H01L27/088 ,  H01L27/098 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/861

Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. A trench isolation structure extends from the first major surface and terminates within the semiconductor region and the floating buried doped region abuts the trench isolation structure. A second doped region is disposed in the first doped region has an opposite conductivity type to the first doped region. A first isolation device is disposed in the first doped region and is configured to divert current injected into the semiconductor device from other regions thereby delaying the triggering of an internal SCR structure. In one embodiment, a second isolation structure is disposed within the first doped region and is configured to disrupt a leakage path along a sidewall surface of the trench isolation structure.

公开(公告)号：US20240387510A1

公开(公告)日：2024-11-21

申请号：US18777737

申请日：2024-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Derrick JOHNSON ,  Yupeng CHEN ,  Ralph N. WALL ,  Mark GRISWOLD

IPC: H01L27/02 ,  H01L27/092

Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

公开(公告)号：US20230361107A1

公开(公告)日：2023-11-09

申请号：US17662263

申请日：2022-05-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Derrick JOHNSON ,  Yupeng CHEN ,  Ralph N. WALL ,  Mark GRISWOLD

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0262 ,  H01L27/0928

Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

公开(公告)号：US20230025410A1

公开(公告)日：2023-01-26

申请号：US17937918

申请日：2022-10-04

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mark GRISWOLD ,  Michael J. SEDDON

IPC: H01L23/522 ,  H01L23/34 ,  H01L21/786 ,  H01L21/02 ,  H01L23/12

Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

公开(公告)号：US20220003800A1

公开(公告)日：2022-01-06

申请号：US17011027

申请日：2020-09-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Alexander STEWART ,  Martin KEJHAR ,  Radim MLCOUSEK ,  Arash ELHAMI KHORASANI ,  David T. PRICE ,  Mark GRISWOLD

IPC: G01R15/14 ,  G01R19/00

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

公开(公告)号：US20250167102A1

公开(公告)日：2025-05-22

申请号：US19028163

申请日：2025-01-17

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Mark GRISWOLD

IPC: H10D86/00 ,  H01L21/304 ,  H01L21/78

Abstract: Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.