公开(公告)号：US20180342549A1

公开(公告)日：2018-11-29

申请号：US16054067

申请日：2018-08-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Bingzhi SU ,  Derek GOCHNOUR ,  Larry KINSMAN

IPC: H01L27/146 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/08 ,  H01L23/31 ,  H01L23/10

CPC classification number: H01L27/14618 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/08 ,  H01L23/10 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/564 ,  H01L24/13 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16588 ,  H01L2924/1715 ,  H01L2224/13099

Abstract: Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.

公开(公告)号：US20170345862A1

公开(公告)日：2017-11-30

申请号：US15166007

申请日：2016-05-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Larry KINSMAN ,  Yu-Te HSIEH ,  Chi-Yao KUO

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a first semiconductor die coupled to a first side of a substrate having one or more internal traces. One or more connectors coupled to the first semiconductor die and the first side of the substrate. A glass lid coupled to the first side of the substrate over the first semiconductor die. A mold compound that encapsulates at least a portion of the substrate. A second semiconductor die coupled to a second side of the substrate opposing the first side. The second semiconductor die is electrically coupled with the first semiconductor die through the one or more traces of the substrate.

公开(公告)号：US20170345864A1

公开(公告)日：2017-11-30

申请号：US15168828

申请日：2016-05-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Larry KINSMAN ,  Yusheng LIN ,  Yu-Te HSIEH ,  Oswald SKEETE ,  Weng-Jin WU ,  Chi-Yao KUO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/498 ,  H04N5/374 ,  H01L21/48

CPC classification number: H01L27/14643 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/49838 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/24 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/181 ,  H04N5/374 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

公开(公告)号：US20190229144A1

公开(公告)日：2019-07-25

申请号：US16374720

申请日：2019-04-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Larry KINSMAN ,  Yusheng LIN ,  Yu-Te HSIEH ,  Oswald SKEETE ,  Weng-Jin WU ,  Chi-Yao KUO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/498 ,  H04N5/374 ,  H01L21/48

Abstract: An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

公开(公告)号：US20180019275A1

公开(公告)日：2018-01-18

申请号：US15674738

申请日：2017-08-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Bingzhi SU ,  Derek GOCHNOUR ,  Larry KINSMAN

IPC: H01L27/146 ,  H01L23/31 ,  H01L21/56 ,  H01L23/10 ,  H01L23/08 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L27/14618 ,  H01L21/4803 ,  H01L21/561 ,  H01L23/08 ,  H01L23/10 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/564 ,  H01L24/13 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16588 ,  H01L2924/1715 ,  H01L2224/13099

Abstract: Implementations of semiconductor packages may include: a die coupled to a glass lid; one or more inner walls having a first material coupled to the die; an outer wall having a second material coupled to the die; and a glass lid coupled to the die at the one or more inner walls and at the outer wall; wherein the outer wall may be located at the edge of the die and the glass lid and the one or more inner walls may be located within the perimeter of the outer wall at a predetermined distance from the perimeter of the outer wall; and wherein a modulus of the first material may be lower than a modulus of the second material.