公开(公告)号：US20250038066A1

公开(公告)日：2025-01-30

申请号：US18359259

申请日：2023-07-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shutesh KRISHNAN ,  Chee Hiong CHEW ,  Yusheng LIN ,  Roveendra PAUL

IPC: H01L23/373 ,  H01L23/427

Abstract: In a general aspect, a semiconductor device assembly includes a metallic chamber configured to transfer thermal energy from a first surface of the metallic chamber to a second surface of the metallic chamber opposite the first surface, a thermally conductive polymer layer disposed on the first surface of the metallic chamber, a patterned metal layer disposed on the thermally conductive polymer layer, and at least one semiconductor die disposed on the patterned metal layer.

公开(公告)号：US20240222231A1

公开(公告)日：2024-07-04

申请号：US18608662

申请日：2024-03-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE ,  Huibin CHEN

IPC: H01L23/492 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/492 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/14 ,  H01L23/49811 ,  H01L23/50 ,  H01L24/06 ,  H01L24/14 ,  H01L23/3735 ,  H01L23/5383 ,  H01L25/18

Abstract: A semiconductor die includes an electronic device formed in the semiconductor die. The semiconductor die further includes a plurality of device contact pads disposed on a surface of the semiconductor die. The plurality of device contact pads are electrically connected to the electronic device. The plurality of device contact pads include at least an emitter contact pad and a signal sense contact pad, and a dummy device contact pad disposed on the surface of the semiconductor die. The dummy device contact pad provides an area for a solder joint between the semiconductor die and a substrate in addition to an area provided by the plurality of device contact pads.

公开(公告)号：US20240072008A1

公开(公告)日：2024-02-29

申请号：US18503513

申请日：2023-11-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/11 ,  H01L29/739 ,  H10N30/50

CPC classification number: H01L25/071 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H10N30/50 ,  H01L23/5385 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US20220375833A1

公开(公告)日：2022-11-24

申请号：US17816455

申请日：2022-08-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Roger Paul STOUT ,  Chee Hiong CHEW ,  Sadamichi TAKAKUSAKI ,  Francis J. CARNEY

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  C04B37/02 ,  H01L23/14 ,  H01L23/373 ,  H01L23/538 ,  H01L23/31

Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

公开(公告)号：US20220359360A1

公开(公告)日：2022-11-10

申请号：US17661420

申请日：2022-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/768 ,  H01L25/00

Abstract: A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.

公开(公告)号：US20220208635A1

公开(公告)日：2022-06-30

申请号：US17136286

申请日：2020-12-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

IPC: H01L23/367 ,  H01L23/373 ,  H01L21/48

Abstract: A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.

公开(公告)号：US20220199502A1

公开(公告)日：2022-06-23

申请号：US17126433

申请日：2020-12-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL ,  Chee Hiong CHEW ,  Yusheng LIN

IPC: H01L23/498 ,  H01L25/18 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48

Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

公开(公告)号：US20220181192A1

公开(公告)日：2022-06-09

申请号：US17652877

申请日：2022-02-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Noboru OKUBO ,  Yusheng LIN

IPC: H01L21/687 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L29/739 ,  H01L29/861

Abstract: At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

公开(公告)号：US20210305096A1

公开(公告)日：2021-09-30

申请号：US17304136

申请日：2021-06-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： George CHANG ,  Yusheng LIN ,  Gordon M. GRIVNA ,  Takashi NOMA

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

公开(公告)号：US20210225797A1

公开(公告)日：2021-07-22

申请号：US17220661

申请日：2021-04-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Huibin CHEN

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/373 ,  H01L21/56

Abstract: In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.