公开(公告)号：US20210013176A1

公开(公告)日：2021-01-14

申请号：US16661633

申请日：2019-10-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Shunsuke YASUDA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/02

Abstract: A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.

公开(公告)号：US20240186285A1

公开(公告)日：2024-06-06

申请号：US18444221

申请日：2024-02-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Shunsuke YASUDA

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L24/94 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/561 ,  H01L2021/60015 ,  H01L2224/94

Abstract: A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.

公开(公告)号：US20240120355A1

公开(公告)日：2024-04-11

申请号：US18473659

申请日：2023-09-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gregg BARDEL ,  Shih-Chang TAI ,  Shunsuke YASUDA ,  Weng-Jin WU

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14685

Abstract: Implementations of a cover for an image sensor may include an optically transmissive portion and a black mask layer applied as a strip adjacent a perimeter of a largest planar surface of the optically transmissive portion. The first edge of the strip closest to the perimeter may be separated from the perimeter by a predetermined distance.

公开(公告)号：US20220131002A1

公开(公告)日：2022-04-28

申请号：US16949321

申请日：2020-10-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Yusheng LIN ,  Kazuo OKADA ,  Hideaki YOSHIMI ,  Shunsuke YASUDA

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/66

Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.