公开(公告)号：US20250149449A1

公开(公告)日：2025-05-08

申请号：US19011340

申请日：2025-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20210035807A1

公开(公告)日：2021-02-04

申请号：US17072521

申请日：2020-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Michael J. SEDDON ,  Francis J. CARNEY ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

公开(公告)号：US20250149450A1

公开(公告)日：2025-05-08

申请号：US19011366

申请日：2025-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20240404879A1

公开(公告)日：2024-12-05

申请号：US18492867

申请日：2023-10-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Takashi NOMA ,  Shinzo ISHIBE

IPC: H01L21/768 ,  C23C18/30 ,  C23C18/42 ,  H01L21/683

Abstract: Implementations of a method of electroless deposition may include providing a semiconductor substrate including a first largest planar surface and a second largest planar surface; forming a backmetal layer on the second largest planar surface; attaching a tape over the backmetal layer; and electroless depositing a metal layer on a pad included on the first largest planar surface. The method may include, after electroless depositing, removing the tape; and after removing the tape, baking the semiconductor substrate.

公开(公告)号：US20240290736A1

公开(公告)日：2024-08-29

申请号：US18175079

申请日：2023-02-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Shinzo ISHIBE ,  Takashi NOMA

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664

Abstract: Implementations of a method of forming an over pad metallization structure may include providing a semiconductor substrate including a plurality of copper pads on a first side of the semiconductor substrate; electroless plating an over pad metallization including nickel, palladium, and gold onto each copper pad of the plurality of copper pads; and patterning a layer of photoresist onto the over pad metallization of each copper pad of the plurality of copper pads. The method may include forming a mold compound over the plurality of copper pads, the over pad metallization, and the layer of photoresist of each copper pad; removing a portion of the mold compound and a portion of the layer of photoresist of each copper pad of the plurality of copper pads; and removing the layer of photoresist to expose the over pad metallization of each copper pad of the plurality of copper pads.

公开(公告)号：US20200243366A1

公开(公告)日：2020-07-30

申请号：US16505949

申请日：2019-07-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA

IPC: H01L21/68 ,  H01L21/78 ,  H01L23/544

Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.

公开(公告)号：US20190287913A1

公开(公告)日：2019-09-19

申请号：US15921898

申请日：2018-03-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20230238327A1

公开(公告)日：2023-07-27

申请号：US18193977

申请日：2023-03-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53233 ,  H01L24/33 ,  H01L24/11

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20220384204A1

公开(公告)日：2022-12-01

申请号：US17808338

申请日：2022-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Michael J. SEDDON ,  Yusheng LIN ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/3065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

公开(公告)号：US20220319894A1

公开(公告)日：2022-10-06

申请号：US17808716

申请日：2022-06-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Takashi NOMA

IPC: H01L21/68 ,  H01L23/544 ,  H01L21/78

Abstract: Implementations of a method of making a plurality of alignment marks on a wafer may include: providing a wafer including an alignment feature on a first side of the wafer. The method may include aligning the wafer using a camera focused on the first side of the wafer. The wafer may be aligned using the alignment feature on the first side of the die. The wafer may also include creating a plurality of alignment marks on a second side of the wafer through lasering, sawing, or scribing.