公开(公告)号：US20250149449A1

公开(公告)日：2025-05-08

申请号：US19011340

申请日：2025-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20250149425A1

公开(公告)日：2025-05-08

申请号：US19019071

申请日：2025-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Jefferson W. HALL ,  Michael J. SEDDON

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H02M3/158 ,  H10D62/13 ,  H10D84/83 ,  H10D89/10 ,  H10F39/00 ,  H10F99/00

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US20240006266A1

公开(公告)日：2024-01-04

申请号：US18469615

申请日：2023-09-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Erik Nino Mercado TOLENTINO ,  Shutesh KRISHNAN ,  Francis J. CARNEY

IPC: H01L23/373 ,  B22F7/06 ,  H01L21/48

CPC classification number: H01L23/3735 ,  B22F7/064 ,  H01L21/4882 ,  B22F2301/10 ,  H01L24/09

Abstract: A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

公开(公告)号：US20220246434A1

公开(公告)日：2022-08-04

申请号：US17660477

申请日：2022-04-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/12

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

公开(公告)号：US20210327843A1

公开(公告)日：2021-10-21

申请号：US17304715

申请日：2021-06-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/482 ,  H01L21/683

Abstract: A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

公开(公告)号：US20210035807A1

公开(公告)日：2021-02-04

申请号：US17072521

申请日：2020-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Michael J. SEDDON ,  Francis J. CARNEY ,  Takashi NOMA ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

公开(公告)号：US20200279747A1

公开(公告)日：2020-09-03

申请号：US16879378

申请日：2020-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Francis J. CARNEY ,  Yusheng LIN ,  Michael J. SEDDON ,  Chee Hiong CHEW ,  Soon Wei WANG ,  Eiji KUROSE

IPC: H01L21/302 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/12 ,  H01L23/00 ,  H01L21/78

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

公开(公告)号：US20200258751A1

公开(公告)日：2020-08-13

申请号：US16861810

申请日：2020-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Eiji KUROSE ,  Chee Hiong CHEW ,  Soon Wei WANG

IPC: H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L21/48 ,  H01L23/31

Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

公开(公告)号：US20190252275A1

公开(公告)日：2019-08-15

申请号：US16396904

申请日：2019-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/055 ,  H01L23/498 ,  H01L23/053 ,  H01L25/07 ,  H01L23/04 ,  H01L23/492 ,  H01L21/50 ,  H01L23/00 ,  H01R4/48 ,  H01L23/50 ,  H01L23/10 ,  H01L23/057

CPC classification number: H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

公开(公告)号：US20190035718A1

公开(公告)日：2019-01-31

申请号：US16148563

申请日：2018-10-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY ,  Eric WOOLSEY

IPC: H01L23/498 ,  H01L21/683

Abstract: A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.