公开(公告)号：US20240016044A1

公开(公告)日：2024-01-11

申请号：US18370616

申请日：2023-09-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

IPC: H10K59/131 ,  H10K59/12

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K59/8722

Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

公开(公告)号：US20220059809A1

公开(公告)日：2022-02-24

申请号：US17519051

申请日：2021-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

IPC: H01L51/56 ,  H01L27/32 ,  H01L33/36 ,  H01L51/52

Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the lime of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

公开(公告)号：US09917274B2

公开(公告)日：2018-03-13

申请号：US15351748

申请日：2016-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideto Ohnuma ,  Noriko Miyairi ,  Naoyuki Senda

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/00 ,  H01L51/50 ,  H01L51/56

CPC classification number: H01L51/5206 ,  H01L27/3246 ,  H01L27/326 ,  H01L51/0002 ,  H01L51/0021 ,  H01L51/0052 ,  H01L51/0054 ,  H01L51/0058 ,  H01L51/006 ,  H01L51/0072 ,  H01L51/0074 ,  H01L51/0085 ,  H01L51/5012 ,  H01L51/52 ,  H01L51/5203 ,  H01L51/5221 ,  H01L51/56 ,  H01L2251/558

Abstract: To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0).

公开(公告)号：US20170062754A1

公开(公告)日：2017-03-02

申请号：US15351748

申请日：2016-11-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideto Ohnuma ,  Noriko MIYAIRI ,  Naoyuki SENDA

IPC: H01L51/52 ,  H01L51/56 ,  H01L27/32 ,  H01L51/50

CPC classification number: H01L51/5206 ,  H01L27/3246 ,  H01L27/326 ,  H01L51/0002 ,  H01L51/0021 ,  H01L51/0052 ,  H01L51/0054 ,  H01L51/0058 ,  H01L51/006 ,  H01L51/0072 ,  H01L51/0074 ,  H01L51/0085 ,  H01L51/5012 ,  H01L51/52 ,  H01L51/5203 ,  H01L51/5221 ,  H01L51/56 ,  H01L2251/558

Abstract: To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0).

Abstract translation: 提供抑制串扰发生的发光面板。 提供抑制串扰发生的发光面板的制造方法。 发光面板包括一个发光元件的第一电极，另一个发光元件的第一电极和分离两个第一电极的绝缘隔板。 包括厚度A1小于包含与隔板的侧表面重叠的发光有机化合物的层的一部分的厚度A0的部分。 第二电极的与隔板的侧面重叠的部分的厚度B1与第一电极重叠的部分的厚度B0的比（B1 / B0）更高 比（A1 / A0）。

公开(公告)号：US09576986B2

公开(公告)日：2017-02-21

申请号：US14340717

申请日：2014-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masayuki Sakakura ,  Hideto Ohnuma ,  Hideaki Kuwabara

IPC: G02F1/136 ,  H01L29/04 ,  H01L27/12 ,  H01L21/768 ,  H01L23/528 ,  H01L27/32

CPC classification number: H01L27/1244 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76886 ,  H01L23/528 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3276 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

Abstract translation: 本发明的目的是提供一种防止接触不良而不增加步数的方法，从而形成具有高驱动性能和可靠性的集成电路。 本发明应用了一种光掩模或掩模版，每个光掩模或光掩模具有衍射光栅图案或由具有光强度降低功能的半透明膜形成的辅助图案，用于在光刻步骤中形成导线的重叠部分 电线 并且形成用作二层结构的下导线的导电膜，然后形成抗蚀剂图案，使得形成下线的第一层和比第一层窄的第二层以缓解 陡峭的一步。

公开(公告)号：US08951878B2

公开(公告)日：2015-02-10

申请号：US14097793

申请日：2013-12-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiro Jinbo ,  Hironobu Shoji ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/84 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26506 ,  H01L21/76254

Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

Abstract translation: 本发明的目的是提供一种制造具有SOI层的SOI衬底的方法，该SOI衬底即使在使用诸如玻璃衬底或塑料衬底的柔性衬底时，也可以在实际应用中以高产率使用。 此外，本发明的另一个目的是提供一种以高产率制造使用这种SOI衬底的薄半导体器件的方法。 当将单晶半导体衬底接合到具有绝缘表面的柔性衬底并且分离单晶半导体衬底以制造SOI衬底时，一个或两个键合表面被激活，然后柔性衬底具有绝缘表面 并且单晶半导体衬底彼此附接。

公开(公告)号：US20130248920A1

公开(公告)日：2013-09-26

申请号：US13892438

申请日：2013-05-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

IPC: H01L33/36

CPC classification number: H01L51/56 ,  H01L27/3241 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L33/36 ,  H01L51/0011 ,  H01L51/52 ,  H01L2251/5338

Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

公开(公告)号：US09812217B2

公开(公告)日：2017-11-07

申请号：US15091762

申请日：2016-04-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Hideto Ohnuma ,  Kei Takahashi

IPC: H01L27/108 ,  G11C19/28 ,  G09G3/20 ,  G09G5/00 ,  H01L21/77 ,  H01L27/12

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G5/00 ,  G09G2310/0248 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2330/021 ,  G09G2380/02 ,  H01L21/77 ,  H01L27/1203 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1266

Abstract: Disclosed is a driver circuit including a latch circuit, a shift register circuit, and a switching circuit, where the latch circuit is provided over the shift register circuit and the switching circuit. The shift register circuit and the switching circuit may have a silicon-based semiconductor, while the latch circuit may have an oxide semiconductor. The latch circuit includes a first transistor and a second transistor connected in series. The latch circuit may further include a first capacitor and a second capacitor which are electrically connected to the first transistor and the second transistor. A display device using the driver circuit as well as a method for preparing the driver circuit is also disclosed.

公开(公告)号：US09502676B2

公开(公告)日：2016-11-22

申请号：US14858282

申请日：2015-09-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideto Ohnuma ,  Noriko Miyairi ,  Naoyuki Senda

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/00 ,  H01L51/50 ,  H01L51/56

CPC classification number: H01L51/5206 ,  H01L27/3246 ,  H01L27/326 ,  H01L51/0002 ,  H01L51/0021 ,  H01L51/0052 ,  H01L51/0054 ,  H01L51/0058 ,  H01L51/006 ,  H01L51/0072 ,  H01L51/0074 ,  H01L51/0085 ,  H01L51/5012 ,  H01L51/52 ,  H01L51/5203 ,  H01L51/5221 ,  H01L51/56 ,  H01L2251/558

Abstract: To provide a light-emitting panel in which the occurrence of crosstalk is suppressed. To provide a method for manufacturing a light-emitting panel in which the occurrence of crosstalk is suppressed. The light-emitting panel includes a first electrode of one light-emitting element, a first electrode of the other light-emitting element, and an insulating partition which separates the two first electrodes. A portion with a thickness A1 smaller than a thickness A0 of a portion of the layer containing a light-emitting organic compound, which overlaps with a side surface of the partition, is included. The ratio (B1/B0) of a thickness B1 of a portion of the second electrode, which overlaps with a side surface of the partition, to a thickness B0 of a portion of the second electrode, which overlaps with the first electrode, is higher than the ratio (A1/A0).

公开(公告)号：US09431431B2

公开(公告)日：2016-08-30

申请号：US14070976

申请日：2013-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

IPC: H01L27/14 ,  H01L27/12 ,  G02F1/1345 ,  H01L29/45 ,  H01L29/786 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.