REGULATOR CIRCUIT WITH ENHANCED RIPPLE REDUCTION SPEED
    1.
    发明申请
    REGULATOR CIRCUIT WITH ENHANCED RIPPLE REDUCTION SPEED 审中-公开
    具有增强纹波降低速度的调节器电路

    公开(公告)号:US20170063217A1

    公开(公告)日:2017-03-02

    申请号:US14840257

    申请日:2015-08-31

    IPC分类号: H02M1/14 G05F1/575

    摘要: A regulator circuit includes an OP-amp, buffer, power transistor, voltage divider, load, and feedback current generator. The OP-amp generates first voltage signal by amplifying a difference between an input voltage signal and a feedback voltage signal. The OP-amp drives a first node as the first voltage signal. The buffer drives a second node as a second voltage signal generated based on the first voltage signal. The power transistor includes a drain terminal receiving a supply voltage, a gate terminal connected to the second node, and a source terminal connected to a third node. The voltage divider generates the feedback voltage signal by dividing an output voltage signal of the third node. The load includes a terminal connected to the third node and another terminal receiving a ground voltage. The feedback current generator provides a first feedback current corresponding to a ripple of the output voltage signal to the first node for enhancing a speed at which the ripple reduced.

    摘要翻译: 调节器电路包括OP放大器,缓冲器,功率晶体管,分压器,负载和反馈电流发生器。 OP放大器通过放大输入电压信号和反馈电压信号之间的差异来产生第一电压信号。 OP-amp驱动第一个节点作为第一个电压信号。 缓冲器驱动第二节点作为基于第一电压信号产生的第二电压信号。 功率晶体管包括接收电源电压的漏极端子,连接到第二节点的栅极端子和连接到第三节点的源极端子。 分压器通过分压第三节点的输出电压信号来产生反馈电压信号。 负载包括连接到第三节点的终端和接收地电压的另一终端。 反馈电流发生器提供对应于第一节点的输出电压信号的纹波的第一反馈电流,以增加纹波减小的速度。