PROTECTION TO AVOID ABNORMAL OPERATION CAUSED BY A SHORTED PARAMETER SETTING PIN OF AN INTEGRATED CIRCUIT
    1.
    发明申请
    PROTECTION TO AVOID ABNORMAL OPERATION CAUSED BY A SHORTED PARAMETER SETTING PIN OF AN INTEGRATED CIRCUIT 有权
    避免由集成电路的短路参数设置引脚引起的异常操作的保护

    公开(公告)号:US20110261492A1

    公开(公告)日:2011-10-27

    申请号:US13092282

    申请日:2011-04-22

    IPC分类号: H02H3/26

    CPC分类号: H02M1/32

    摘要: For a system to avoid abnormal operation caused by a shorted parameter setting pin of an integrated circuit, a protection apparatus and method apply a buffered reference voltage to the parameter setting pin to define an internal parameter of the integrated circuit by the buffered reference voltage and an external element connected to the parameter setting pin, and detect the rapid variation of the internal parameter to trigger a shutdown signal or slow down the speed of the variation of the internal parameter reflected to an adjustable signal of the integrated circuit.

    摘要翻译: 为了避免由集成电路的短路参数设置引脚引起的异常操作的系统,保护装置和方法将缓冲的参考电压施加到参数设置引脚,以通过缓冲的参考电压定义集成电路的内部参数,并且 外部元件连接到参数设置引脚,并检测内部参数的快速变化以触发关断信号或将内部参数变化的速度降低到集成电路的可调信号。

    PHASE INTERLEAVING CONTROL METHOD FOR A MULTI-CHANNEL REGULATOR SYSTEM
    2.
    发明申请
    PHASE INTERLEAVING CONTROL METHOD FOR A MULTI-CHANNEL REGULATOR SYSTEM 有权
    用于多通道调节器系统的相位交互控制方法

    公开(公告)号:US20110260765A1

    公开(公告)日:2011-10-27

    申请号:US13087466

    申请日:2011-04-15

    IPC分类号: H03K3/289

    摘要: A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls its operation mode according to whether or not an external clock is detected. Therefore, each channel will not be limited to operate under a constant mode and could become a master channel or a slave channel. Additionally, each of the PWM integrated circuits generates a phase shifted synchronous clock for its next channel during it is enabled, and thus all the channels operate in a synchronous but phase interleaving manner.

    摘要翻译: 多通道稳压器系统包括串联连接的PWM集成电路,每个PWM集成电路确定用于相应通道的PWM信号以进行操作,并且根据是否检测到外部时钟单独地控制其操作模式。 因此,每个通道不限于在恒定模式下工作,并且可以成为主通道或从通道。 此外,每个PWM集成电路在其使能期间产生用于其下一个通道的相移同步时钟,因此所有通道以同步但相位交错的方式工作。

    REAL TIME ADJUSTABLE ZERO CURRENT DETECTION FOR A SWITCHING REGULATOR
    3.
    发明申请
    REAL TIME ADJUSTABLE ZERO CURRENT DETECTION FOR A SWITCHING REGULATOR 有权
    用于开关稳压器的实时可调零电流检测

    公开(公告)号:US20110267015A1

    公开(公告)日:2011-11-03

    申请号:US13093205

    申请日:2011-04-25

    IPC分类号: G05F1/618

    摘要: A feedback loop is used to optimize a zero current threshold for a switching regulator. After the low side power switch of the switching regulator turns off, the switching node state is monitored to adjust the zero current threshold in a real time and thus the low-side power switch is prevented from turning off too early or too late. Thereby the efficiency in green mode is optimized.

    摘要翻译: 反馈回路用于优化开关稳压器的零电流阈值。 在开关稳压器的低侧电源开关关断后,监视开关节点状态,实时调整零电流阈值,防止低端电源开关过早关断。 从而优化了绿色模式的效率。

    POWER OFF DELAY CIRCUIT AND METHOD, AND AUDIO SYSTEM WITH POWER OFF DELAY
    4.
    发明申请
    POWER OFF DELAY CIRCUIT AND METHOD, AND AUDIO SYSTEM WITH POWER OFF DELAY 审中-公开
    断电延迟电路和方法,以及带电源延时的音频系统

    公开(公告)号:US20130063216A1

    公开(公告)日:2013-03-14

    申请号:US13644434

    申请日:2012-10-04

    IPC分类号: H03F1/30

    摘要: A power off delay circuit includes a switch connected between an external power input terminal and an internal power supply terminal, a capacitor connected to the internal power supply terminal, and a hysteresis comparator to switch the switch according to the voltages of the external power input terminal and the internal power supply terminal. During on-time of the switch, the external power input terminal is connected to the internal power supply terminal and the capacitor can be charged by the external power source. When the switch is off, the capacitor provides electric power for an internal circuit. Application of the power off delay circuit to an audio system may eliminate the turn-off pops of the audio system.

    摘要翻译: 断电延迟电路包括连接在外部电源输入端子和内部电源端子之间的开关,连接到内部电源端子的电容器和滞后比较器,用于根据外部电力输入端子的电压来切换开关 和内部电源端子。 在接通时,外部电源输入端子连接到内部电源端子,电容器可以通过外部电源充电。 当开关关闭时,电容为内部电路提供电力。 将断电延迟电路应用于音频系统可以消除音频系统的关闭声音。

    POWER OFF DELAY CIRCUIT AND METHOD, AND AUDIO SYSTEM WITH POWER OFF DELAY
    5.
    发明申请
    POWER OFF DELAY CIRCUIT AND METHOD, AND AUDIO SYSTEM WITH POWER OFF DELAY 失效
    断电延迟电路和方法,以及带电源延时的音频系统

    公开(公告)号:US20100320844A1

    公开(公告)日:2010-12-23

    申请号:US12818539

    申请日:2010-06-18

    IPC分类号: H02B1/24

    摘要: A power off delay circuit includes a switch connected between an external power input terminal and an internal power supply terminal, a capacitor connected to the internal power supply terminal, and a hysteresis comparator to switch the switch according to the voltages of the external power input terminal and the internal power supply terminal. During on-time of the switch, the external power input terminal is connected to the internal power supply terminal and the capacitor can be charged by the external power source. When the switch is off, the capacitor provides electric power for an internal circuit. Application of the power off delay circuit to an audio system may eliminate the turn-off pops of the audio system.

    摘要翻译: 断电延迟电路包括连接在外部电源输入端子和内部电源端子之间的开关,连接到内部电源端子的电容器和滞后比较器,用于根据外部电力输入端子的电压来切换开关 和内部电源端子。 在接通时,外部电源输入端子连接到内部电源端子,电容器可以通过外部电源充电。 当开关关闭时,电容为内部电路提供电力。 将断电延迟电路应用于音频系统可以消除音频系统的关闭声音。

    SIMPLE INTERLEAVED PHASE SHIFT CLOCK SYNCHRONIZATION FOR MASTER/SLAVE SCHEME
    6.
    发明申请
    SIMPLE INTERLEAVED PHASE SHIFT CLOCK SYNCHRONIZATION FOR MASTER/SLAVE SCHEME 失效
    用于主/从动方案的简单的交互式相移时钟同步

    公开(公告)号:US20110163785A1

    公开(公告)日:2011-07-07

    申请号:US12977662

    申请日:2010-12-23

    IPC分类号: H03L7/00 G06F1/04

    CPC分类号: G06F1/04

    摘要: An apparatus for interleaved phase shift clock synchronization includes a master clock generator and at least one slave clock generator. The master clock generator provides a ramp signal or reset signal for each slave clock generator to generate a clock synchronized with the clock of the master clock generator, and the master and slave clock generators have different reference voltages for generating clocks. Therefore, the clocks generated will be synchronized and interleaved phase with each other.

    摘要翻译: 用于交错相移时钟同步的装置包括主时钟发生器和至少一个从时钟发生器。 主时钟发生器为每个从时钟发生器提供斜坡信号或复位信号,以产生与主时钟发生器的时钟同步的时钟,并且主时钟和从时钟发生器具有不同的参考电压用于产生时钟。 因此,产生的时钟将彼此同步并交错相位。

    CONSTANT FREQUENCY ON-TIME CONTROL SYSTEM AND METHOD AND VOLTAGE REGULATOR USING THE SAME
    7.
    发明申请
    CONSTANT FREQUENCY ON-TIME CONTROL SYSTEM AND METHOD AND VOLTAGE REGULATOR USING THE SAME 有权
    恒定频率时间控制系统及使用该方法的电压调节器

    公开(公告)号:US20120249108A1

    公开(公告)日:2012-10-04

    申请号:US13181686

    申请日:2011-07-13

    IPC分类号: G05F5/00

    CPC分类号: H02M3/156

    摘要: A constant frequency ON-time control system applied to a voltage regulator is disclosed. The voltage regulator determines a time length of an input voltage inputted thereto according to an ON-time and thereby regulates an output voltage. The constant frequency ON-time control system includes a constant frequency ON-time control circuit for computing the ON-time according to a system duty cycle of the voltage regulator and a frequency setting parameter and a frequency setting parameter adjusting circuit for generating a frequency setting parameter adjust value according to an OFF-time corresponding to the ON-time and taking a result of operation between the frequency setting parameter adjust value and a preset frequency setting parameter as the frequency setting parameter. The frequency setting parameter adjusting circuit uses the frequency setting parameter adjust value to change the result of operation for varying the frequency setting parameter when the OFF-time is shorter than a reference value.

    摘要翻译: 公开了一种应用于电压调节器的恒定频率ON时间控制系统。 电压调节器根据接通时间确定输入电压的输入电压的时间长度,从而调节输出电压。 恒频接通时间控制系统包括:恒定频率接通时间控制电路,用于根据电压调节器的系统占空比计算接通时间;频率设定参数;频率设定参数调整电路,用于产生频率设定 根据与导通时间对应的关闭时间进行参数调整,并且将频率设定参数调整值与预设频率设定参数之间的运算结果作为频率设定参数。 频率设定参数调整电路使用频率设定参数调整值,在OFF时间比基准值短的情况下,改变频率设定参数的动作结果。

    HYSTERETIC MODE LED DRIVER WITH PRECISE AVERAGE CURRENT
    8.
    发明申请
    HYSTERETIC MODE LED DRIVER WITH PRECISE AVERAGE CURRENT 有权
    具有精度平均电流的休眠模式LED驱动器

    公开(公告)号:US20110069056A1

    公开(公告)日:2011-03-24

    申请号:US12885959

    申请日:2010-09-20

    IPC分类号: G06F3/038 G09G3/32

    CPC分类号: H05B33/0851

    摘要: A hysteretic mode LED driver for providing a driving current for an LED includes a hysteretic comparing circuit and a feedback loop. The hysteretic comparing circuit compares a driving current related sensing signal with a reference signal to control the average value of the driving current. The feedback loop senses the error between the average value of the driving current and a target value to adjust the reference signal or the offset of the hysteretic comparing circuit to adjust the average value of the driving current.

    摘要翻译: 用于为LED提供驱动电流的迟滞模式LED驱动器包括迟滞比较电路和反馈回路。 迟滞比较电路将驱动电流相关感测信号与参考信号进行比较,以控制驱动电流的平均值。 反馈回路检测驱动电流的平均值与目标值之间的误差,以调整参考信号或滞后比较电路的偏移量,以调整驱动电流的平均值。

    OFFSET AND DELAY CANCELLATION CIRCUIT FOR A SWITCHING DC-DC POWER SUPPLY
    9.
    发明申请
    OFFSET AND DELAY CANCELLATION CIRCUIT FOR A SWITCHING DC-DC POWER SUPPLY 有权
    用于切换DC-DC电源的偏移和延迟断开电路

    公开(公告)号:US20120025793A1

    公开(公告)日:2012-02-02

    申请号:US13188867

    申请日:2011-07-22

    IPC分类号: G05F1/00

    CPC分类号: H02M3/156

    摘要: A control circuit and method of a switching DC-DC power supply detects the error between the output voltage of the power supply and a design value of the output voltage and according to the error, determines an offset adjust signal to adjust the offset of an error comparator of the power supply to pull the output voltage toward the design value.

    摘要翻译: 开关DC-DC电源的控制电路和方法检测电源的输出电压和输出电压的设计值之间的误差,并根据误差,确定偏移调整信号以调整误差的偏移 电源的比较器将输出电压拉至设计值。