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    METHOD OF FORMING STRAINED CMOS TRANSISTOR
    3.
    发明申请
    METHOD OF FORMING STRAINED CMOS TRANSISTOR 审中-公开
    形成应变CMOS晶体管的方法

    公开(公告)号：US20080206943A1

    公开(公告)日：2008-08-28

    申请号：US11679132

    申请日：2007-02-26

    申请人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai

    发明人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L29/7843

    摘要： A method of fabricating CMOS transistor is disclosed. Initially, a semiconductor substrate having at least a first active area and a second active area is provided. A high-strained thin film is formed on the semiconductor substrate, the first active area, and the second active area. Thereafter, a mask is formed to cover a part of the high-strained thin film, which is disposed on the first active area. An implantation is performed to implant dopants into the part of the high-strained thin film on the second active area and to modify the stress status thereof. After that, the mask is removed and a rapid thermal annealing process is performed. Then, the high-strained thin film is removed and the method of the present invention is accomplished.

    摘要翻译： 公开了制造CMOS晶体管的方法。 首先，提供至少具有第一有源区和第二有源区的半导体衬底。 在半导体衬底，第一有源区和第二有源区上形成高应变薄膜。 此后，形成掩模以覆盖布置在第一有源区上的高应变薄膜的一部分。 进行注入以将掺杂剂注入到第二有源区上的高应变薄膜的一部分中并修改其应力状态。 之后，除去掩模并进行快速热退火处理。 然后，去除高应变薄膜，完成本发明的方法。

    Chemical Vapor Deposition Method Preventing Particles Forming in Chamber
    4.
    发明申请
    Chemical Vapor Deposition Method Preventing Particles Forming in Chamber 有权
    化学气相沉积法防止在室内形成颗粒

    公开(公告)号：US20060234518A1

    公开(公告)日：2006-10-19

    申请号：US10907857

    申请日：2005-04-18

    申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    IPC分类号： H01L21/31 ,  C23C16/40

    CPC分类号： C23C16/4404 ,  H01J37/32082

    摘要： Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency bias is provided to the chamber. The high-power LFRF is continuously provided to the chamber to sustain the temperature of the chamber, and then a main oxide layer deposition process is performed. The method is able to form an oxide layer of better quality on a CVD chamber wall, so as to solve the particle problem in the prior art. Therefore, yield is improved and the maintenance cost is reduced.

    摘要翻译： 防止化学气相沉积（CVD）室受到颗粒污染的影响，其中提供较高的低频射频功率（LFRF）功率和较长的处理时间以腾出室并执行预热过程。 之后，在室壁上形成预氧化物层，同时向室提供高频射频偏压。 大功率LFRF被连续地提供给室以维持室的温度，然后执行主氧化层沉积工艺。 该方法能够在CVD室壁上形成更好质量的氧化物层，从而解决现有技术中的颗粒问题。 因此，产量提高，维护成本降低。

    Chemical vapor deposition method preventing particles forming in chamber
    5.
    发明授权
    Chemical vapor deposition method preventing particles forming in chamber 有权
    化学气相沉积法防止在室内形成颗粒

    公开(公告)号：US07651960B2

    公开(公告)日：2010-01-26

    申请号：US10907857

    申请日：2005-04-18

    申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    IPC分类号： C23C16/40 ,  B05D3/00 ,  H01L21/469

    CPC分类号： C23C16/4404 ,  H01J37/32082

    摘要： Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency bias is provided to the chamber. The high-power LFRF is continuously provided to the chamber to sustain the temperature of the chamber, and then a main oxide layer deposition process is performed. The method is able to form an oxide layer of better quality on a CVD chamber wall, so as to solve the particle problem in the prior art. Therefore, yield is improved and the maintenance cost is reduced.

    摘要翻译： 防止化学气相沉积（CVD）室受到颗粒污染的影响，其中提供较高的低频射频功率（LFRF）功率和较长的处理时间以腾出室并执行预热过程。 之后，在室壁上形成预氧化物层，同时向室提供高频射频偏压。 大功率LFRF被连续地提供给室以维持室的温度，然后执行主氧化层沉积工艺。 该方法能够在CVD室壁上形成更好质量的氧化物层，从而解决现有技术中的颗粒问题。 因此，产量提高，维护成本降低。

    Method for forming a gate and etching a conductive layer
    6.
    发明授权
    Method for forming a gate and etching a conductive layer 有权
    形成栅极并蚀刻导电层的方法

    公开(公告)号：US07588883B2

    公开(公告)日：2009-09-15

    申请号：US11382470

    申请日：2006-05-09

    申请人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    发明人： Neng-Kuo Chen ,  Teng-Chun Tsai ,  Hsiu-Lien Liao

    IPC分类号： G03F1/00 ,  H01L21/00

    CPC分类号： H01L21/32139 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/31111 ,  H01L29/518

    摘要： A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.

    摘要翻译： 提供一种形成栅极的方法和蚀刻导电层的方法。 首先，在其表面上依次提供包括电介质层和导电层的基板。 随后，在导电层上形成图案化氮化硅层作为硬掩模，并且图案化氮化硅层的氢浓度大于1022原子/ cm3。 此后，使用硬掩模作为掩模蚀刻导电层和电介质层。 最后，使用蚀刻溶液去除硬掩模。

    METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM
    9.
    发明申请
    METHOD AND APPARATUS FOR FABRICATING HIGH TENSILE STRESS FILM 有权
    用于制备高拉应力膜的方法和装置

    公开(公告)号：US20080305600A1

    公开(公告)日：2008-12-11

    申请号：US11758623

    申请日：2007-06-05

    申请人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

    发明人： Hsiu-Lien Liao ,  Neng-Kuo Chen ,  Teng-Chun Tsai ,  Yi-Wei Chen

    IPC分类号： H01L21/336 ,  H01J37/08

    CPC分类号： H01L21/324 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843

    摘要： A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.

    摘要翻译： 用于制造高拉伸应力膜的方法和设备包括提供基板，在基板上形成多应力器，并且执行紫外线快速热处理（UVRTP），用于固化聚应力器并调整其拉伸应力状态，因此 多应力器作为高拉伸应力膜。 由于来自光子和热的能量的组合，高拉伸应力膜的拉伸应力状态在相对较短的工艺周期或相对较低的温度下调节。

    METHOD OF MANUFACTURING A MOS TRANSISTOR DEVICE
    10.
    发明申请
    METHOD OF MANUFACTURING A MOS TRANSISTOR DEVICE 审中-公开
    制造MOS晶体管器件的方法

    公开(公告)号：US20080242020A1

    公开(公告)日：2008-10-02

    申请号：US11692912

    申请日：2007-03-28

    申请人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

    发明人： Jei-Ming Chen ,  Neng-Kuo Chen ,  Hsiu-Lien Liao ,  Teng-Chun Tsai ,  Chien-Chung Huang ,  Shih-Wei Sun

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/0217 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

    摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor.

    摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 首先制备位于半导体衬底上的半导体衬底和栅极结构。 源极区域和漏极区域包括在栅极结构的两个相对侧上的半导体衬底中。 随后，在半导体衬底上形成应力覆盖层，并覆盖栅极结构，源极区和漏极区。 接下来，进行惰性气体处理以改变应力帽层的应力值。 由于通过本发明可以容易地调整应力覆盖层的应力值，因此可以将一个应力覆盖层施加到N型MOS晶体管和P型MOS晶体管两者。