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公开(公告)号：USRE48275E1
公开(公告)日：2020-10-20
申请号：US15217364
申请日：2016-07-22
发明人： Aaron J. Caffee , Brian G. Drost
摘要： A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.
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公开(公告)号：US10693482B2
公开(公告)日：2020-06-23
申请号：US16020605
申请日：2018-06-27
发明人： Aaron J. Caffee
摘要： A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.
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公开(公告)号：US09634678B1
公开(公告)日：2017-04-25
申请号：US15052985
申请日：2016-02-25
发明人： Aaron J. Caffee , Brian G. Drost , Vaibhav Karkare
CPC分类号： H03L7/187 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/183 , H03L2207/50
摘要： A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.
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公开(公告)号：US20170019269A1
公开(公告)日：2017-01-19
申请号：US14798545
申请日：2015-07-14
发明人： Aaron J. Caffee
IPC分类号： H04L12/423
CPC分类号： H04L12/423
摘要： Techniques for reducing error in time-of-flight measurement due to transceiver latency are disclosed. A method includes determining a first indicator of a first latency of a first transceiver of a first system using a first loopback configuration of the first transceiver. The method includes receiving a second indicator of a second latency of a second transceiver determined by a second system using a second loopback configuration of the second transceiver. The method includes determining a third indicator of a roundtrip latency of a communication from the first transceiver to the second transceiver and back to the first transceiver. The method includes determining a time-of-flight between the first system and the second system based on the first indicator, the second indicator, and the third indicator.
摘要翻译： 披露了由于收发器延迟而减少飞行时间测量误差的技术。 一种方法包括使用第一收发器的第一回送配置来确定第一系统的第一收发器的第一等待时间的第一指示符。 该方法包括使用第二收发器的第二回送配置来接收由第二系统确定的第二收发器的第二等待时间的第二指示符。 该方法包括确定从第一收发器到第二收发器的通信的往返延迟的第三指示符，并且返回到第一收发器。 该方法包括基于第一指示符，第二指示符和第三指示符来确定第一系统和第二系统之间的飞行时间。
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公开(公告)号：US20160373120A1
公开(公告)日：2016-12-22
申请号：US14745545
申请日：2015-06-22
发明人： Aaron J. Caffee , Brian G. Drost
CPC分类号： H03L7/091 , G06F1/022 , H03K5/135 , H03L7/081 , H03L7/0814 , H03L7/0891 , H03L7/093 , H03L7/183 , H03L7/1976
摘要： A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
摘要翻译： 用于校准数字 - 时间转换器的技术包括一种包括数字 - 时间转换器的装置，其被配置为基于数字码，输入信号和增益校准信号来产生输出信号。 输出信号具有基于数字码从输入信号的相应边缘线性延迟的边缘。 数字代码在评估代码和校准代码之间摇摆。 该装置包括被配置为提供输入信号的延迟版本的参考信号发生器。 参考信号发生器的延迟与数字 - 时间转换器的延迟相匹配。 该装置包括校准电路，其被配置为基于输出信号和输入信号的延迟版本来生成增益校准信号。 校准代码可以在第一校准延迟代码和第二校准延迟代码之间交替。
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公开(公告)号：US09473150B2
公开(公告)日：2016-10-18
申请号：US14087993
申请日：2013-11-22
发明人： Aaron J. Caffee
摘要： Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an oscillating signal. The apparatus includes a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current. The feedback loop includes a rectifier circuit configured to generate the current-mode indicator and a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the reference current. The feedback circuit may include a capacitor coupled to the summing node and configured to accumulate charge according to the difference. A magnitude of the current-mode indicator may be at least two orders of magnitude less than a magnitude of the current through an output node of the oscillator circuit.
摘要翻译： 描述了用于振荡器的自动幅度控制的各种技术。 一种装置包括被配置为产生振荡信号的振荡器电路。 该装置包括反馈电路，其被配置为基于振荡信号的峰值幅度和参考电流的电流模式指示来控制振荡器电路的偏置信号，以维持振荡信号的目标峰值振幅。 反馈回路包括被配置为产生电流模式指示器的整流电路和被配置为基于电流模式指示器和参考电流之间的差提供偏置控制信号的求和节点。 反馈电路可以包括耦合到求和节点的电容器，并且被配置成根据该差异累加电荷。 电流模式指示器的幅度可以比通过振荡器电路的输出节点的电流的幅度小至少两个数量级。
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公开(公告)号：US09362936B1
公开(公告)日：2016-06-07
申请号：US14745534
申请日：2015-06-22
发明人： Aaron J. Caffee , Brian G. Drost
摘要： A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.
摘要翻译： 数字 - 时间转换器包括第一节点，被配置为接收参考信号的第二节点和配置成将被动阻抗耦合到第一节点的数模转换信号转换器。 根据数字码选择被动阻抗。 数字到时间转换器还包括第一开关，其被配置为响应于输入信号选择性地将第一节点耦合到第二参考信号，以及配置成基于第一节点上的第一信号生成输出信号的比较器， 参考信号在第二个节点上。 数字到时间转换器可以包括被配置为响应于第一控制信号而选择性地将第一节点耦合到第三参考信号的第二开关。
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公开(公告)号：US20200007138A1
公开(公告)日：2020-01-02
申请号：US16020605
申请日：2018-06-27
发明人： Aaron J. Caffee
摘要： A time-to-voltage converter includes a switched-capacitor circuit configured to charge an output node to a reset voltage level in a first interval of a conversion period and configured to shift a voltage on the output node from the reset voltage level to a shifted reset voltage level in a second interval of the conversion period. The time-to-voltage converter includes a current source selectively coupled to the output node. The current source is configured to provide a constant current to the output node in a third interval of the conversion period. The shifted reset voltage level is outside a voltage range defined by a first power supply voltage level on a first voltage reference node and a second power supply voltage level on a second voltage reference node.
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公开(公告)号：US20200007136A1
公开(公告)日：2020-01-02
申请号：US16022188
申请日：2018-06-28
摘要： A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.
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公开(公告)号：US20200006314A1
公开(公告)日：2020-01-02
申请号：US16019746
申请日：2018-06-27
发明人： Aaron J. Caffee , Brian G. Drost
IPC分类号： H01L27/01 , H03M1/80 , H01L23/522 , H01L49/02
摘要： An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.
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