公开(公告)号：US10296026B2

公开(公告)日：2019-05-21

申请号：US14918651

申请日：2015-10-21

Applicant: Silicon Laboratories Inc.

Inventor： Aaron J. Caffee ,  Vaibhav Karkare

IPC: H03K5/003 ,  G05F1/567 ,  G05F3/20 ,  G05F3/30 ,  H01L35/00 ,  G05F1/46 ,  G05F1/575

Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.

公开(公告)号：US09634678B1

公开(公告)日：2017-04-25

申请号：US15052985

申请日：2016-02-25

Applicant: Silicon Laboratories Inc.

Inventor： Aaron J. Caffee ,  Brian G. Drost ,  Vaibhav Karkare

IPC: H03L7/06 ,  H03L7/187 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093 ,  H03L7/091

CPC classification number: H03L7/187 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/183 ,  H03L2207/50

Abstract: A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.

公开(公告)号：US20170115677A1

公开(公告)日：2017-04-27

申请号：US14918651

申请日：2015-10-21

Applicant: Silicon Laboratories Inc.

Inventor： Aaron J. Caffee ,  Vaibhav Karkare

IPC: G05F1/46 ,  G05F1/575 ,  H03K3/356

CPC classification number: G05F1/468 ,  G05F1/575

Abstract: A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.