公开(公告)号：US20150200358A1

公开(公告)日：2015-07-16

申请号：US14261533

申请日：2014-04-25

Applicant: SK hynix Inc.

Inventor： Se Hun KANG ,  Jin Ha KIM ,  Kang Sik CHOI ,  Deok Sin KIL ,  Gyu Hyun KIM ,  Kyoung Su CHOI ,  Sung Bin HONG ,  Jung Won SEO

IPC: H01L45/00 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L45/06 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1683

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a lower electrode disposed on the semiconductor substrate wherein an upper surface of the lower electrode has a recess, an interlayer insulating layer disposed on the semiconductor substrate and the lower electrode, the interlayer insulating layer including a variable resistive region exposing the upper surface of the lower electrode, and a variable resistive layer filled in the variable resistive region that contacts the recess of the lower electrode. The variable resistive layer is formed to have an increased width toward a top and a bottom thereof.

Abstract translation: 半导体集成电路器件包括半导体衬底，设置在半导体衬底上的下电极，其中下电极的上表面具有凹部，设置在半导体衬底上的层间绝缘层和下电极，所述层间绝缘层包括： 暴露下部电极的上表面的可变电阻区域和填充在与下部电极的凹部接触的可变电阻区域中的可变电阻层。 可变电阻层形成为朝向其顶部和底部具有增加的宽度。

公开(公告)号：US20140054537A1

公开(公告)日：2014-02-27

申请号：US13791468

申请日：2013-03-08

Applicant: SK HYNIX INC.

Inventor： Seung Yun LEE ,  Hae Chan PARK ,  Myoung Sub KIM ,  Sung Bin HONG ,  Se Ho LEE ,  Jung Won SEO

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/16 ,  H01L45/1683

Abstract: A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof.

Abstract translation: 提供能够防止干扰的电阻式存储装置。 电阻式存储器件包括形成在半导体衬底上的下电极，设置在下电极上的可变电阻器，设置在可变电阻器上的上电极以及被配置为使可变电阻器绝缘的层间绝缘层。 层间绝缘层的至少一部分中可以包括气隙区域。

公开(公告)号：US20140166965A1

公开(公告)日：2014-06-19

申请号：US13846129

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Jung Won SEO ,  Hae Chan PARK ,  Myoung Sub KIM ,  Sung Bin HONG ,  Se Ho LEE ,  Seung Yun LEE

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/124 ,  H01L45/1608 ,  H01L45/1666

Abstract: A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure.

Abstract translation: 电阻式存储器件可以包括底部结构，设置在底部结构上的存储单元结构，以及设置成围绕存储单元结构的外侧壁的数据存储材料。