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    NONVOLATILE MEMORY DEVICE HAVING A FERROELECTRIC LAYER
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING A FERROELECTRIC LAYER 有权

    公开(公告)号：US20220278132A1

    公开(公告)日：2022-09-01

    申请号：US17749118

    申请日：2022-05-19

    Applicant: SK hynix Inc.

    Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO ,  Jae Gil LEE

    IPC: H01L27/11597 ,  H01L29/788 ,  H01L29/78 ,  H01L29/786 ,  H01L27/11587

    Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

    NONVOLATILE MEMORY DEVICE INCLUDING FERROELECTRIC LAYER HAVING NEGATIVE CAPACITANCE
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE INCLUDING FERROELECTRIC LAYER HAVING NEGATIVE CAPACITANCE 有权

    公开(公告)号：US20210035990A1

    公开(公告)日：2021-02-04

    申请号：US16821186

    申请日：2020-03-17

    Applicant: SK hynix Inc.

    Inventor： Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

    IPC: H01L27/1159 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

    THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE STRUCTURE AND METHOD OF OPERATING THE SAME
    6.
    发明申请
    THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE STRUCTURE AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210202577A1

    公开(公告)日：2021-07-01

    申请号：US16908635

    申请日：2020-06-22

    Applicant: SK hynix Inc.

    Inventor： Jae Hyun HAN ,  Se Ho LEE ,  Hyangkeun YOO

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

    NONVOLATILE MEMORY DEVICE HAVING A FERROELECTRIC LAYER
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING A FERROELECTRIC LAYER 有权

    公开(公告)号：US20210175253A1

    公开(公告)日：2021-06-10

    申请号：US16891544

    申请日：2020-06-03

    Applicant: SK hynix Inc.

    Inventor： Jae Hyun HAN ,  Jae Gil LEE ,  Hyangkeun YOO ,  Se Ho LEE

    IPC: H01L27/11597 ,  H01L27/11587

    Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

    NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE MEMORY LAYER
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE HAVING RESISTANCE CHANGE MEMORY LAYER 有权

    公开(公告)号：US20210074354A1

    公开(公告)日：2021-03-11

    申请号：US16844662

    申请日：2020-04-09

    Applicant: SK hynix Inc.

    Inventor： Jae Hyun HAN ,  Hyangkeun YOO ,  Se Ho LEE

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

    SEMICONDUCTOR DEVICE INCLUDING INTERLAYER INSULATION STRUCTURE INCLUDING METAL-ORGANIC FRAMEWORK
    10.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING INTERLAYER INSULATION STRUCTURE INCLUDING METAL-ORGANIC FRAMEWORK 有权

    公开(公告)号：US20240381655A1

    公开(公告)日：2024-11-14

    申请号：US18782430

    申请日：2024-07-24

    Applicant: SK hynix Inc.

    Inventor： Won Tae KOO ,  Jae Hyun HAN ,  Se Ho LEE

    IPC: H10B51/20 ,  H01L29/06

    Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.

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