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    Semiconductor integrated circuit apparatus and method of manufacturing the same
    2.
    发明授权
    Semiconductor integrated circuit apparatus and method of manufacturing the same 有权
    半导体集成电路装置及其制造方法

    公开(公告)号：US09224832B2

    公开(公告)日：2015-12-29

    申请号：US14046468

    申请日：2013-10-04

    Applicant: SK hynix Inc.

    Inventor： Joon Seop Sim

    IPC: H01L29/66 ,  H01L27/24

    CPC classification number: H01L29/66666 ,  H01L21/26513 ,  H01L21/30604 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/66628

    Abstract: A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source.

    Abstract translation: 提供一种半导体集成电路装置及其制造方法。 半导体集成电路装置包括具有有源岛的半导体衬底，埋在有源岛的预定部分中的栅极，形成在栅极两侧的源极和漏极以及形成在有源岛中的电流阻挡层对应 到排水管的下部。 当电流从漏极流入时，电流阻挡层被配置为通过源的下部将电流放电到半导体衬底的内部。

    Computing system for determining resource to perform operation on data and operating method thereof
    3.
    发明授权
    Computing system for determining resource to perform operation on data and operating method thereof 有权

    公开(公告)号：US12189551B2

    公开(公告)日：2025-01-07

    申请号：US18072159

    申请日：2022-11-30

    Applicant: SK hynix Inc.

    Inventor： Joon Seop Sim

    IPC: G06F13/28

    Abstract: The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.

    Host performing an embedding operation and computing system including the same
    6.
    发明授权
    Host performing an embedding operation and computing system including the same 有权

    公开(公告)号：US11693569B2

    公开(公告)日：2023-07-04

    申请号：US17506311

    申请日：2021-10-20

    Applicant: SK hynix Inc.

    Inventor： Joon Seop Sim ,  Myung Hyun Rhee

    IPC: G06F3/06

    CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A computing system capable of reducing data movement during an embedding operation and efficiently processing the embedding operation includes a host and a memory system. The host divides a plurality of feature tables, each including a respective plurality of embedding vectors for a respective plurality of elements, into a first feature table group and a second feature table group; generates a first embedding table configured of the first feature table group; and sends a request for a generation operation of a second embedding table configured of the second feature table group to the memory system. The memory system generates the second embedding table according to the generation operation request provided by the host. The host divides the plurality of feature tables into the first feature table group and the second feature table group based on the number of elements included in each of the plurality of feature tables.

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