公开(公告)号：US11515897B2

公开(公告)日：2022-11-29

申请号：US16988026

申请日：2020-08-07

Applicant: SK hynix Inc.

Inventor： Kyoung Lae Cho ,  Soo Jin Kim ,  Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Chenrong Xiong ,  Fan Zhang ,  Yu Cai ,  Abhiram Prabahkar

IPC: H03M13/00 ,  H03M13/37 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

公开(公告)号：US11177835B2

公开(公告)日：2021-11-16

申请号：US16549930

申请日：2019-08-23

Applicant: SK hynix Inc.

Inventor： Kyoung Lae Cho ,  Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin ,  Chenrong Xiong ,  Fan Zhang ,  Yu Cai ,  Abhiram Prabahkar

IPC: H03M13/37 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

公开(公告)号：US11115062B2

公开(公告)日：2021-09-07

申请号：US16355247

申请日：2019-03-15

Applicant: SK hynix Inc.

Inventor： Naveen Kumar ,  Aman Bhatia ,  Fan Zhang

IPC: H03M13/00 ,  H03M13/37 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C16/08 ,  G11C16/04

Abstract: Memory controllers, decoders and methods perform decoding of a codeword comprising multiple bits. For a select one of those bits, which belongs to at least one component codeword of the codeword, at an iteration of decoding, the following operations are performed. Channel information for the select bit is biased based on degree of the select bit. A reliability indicator of an initial decision as to whether to flip the select bit is computed based on the initial decision and the biased channel information. The reliability indicator is compared with an adaptive threshold, which is determined based on the degree of the select bit and unsatisfied check (USC) information from the initial decision. A decision is then made as to whether to flip the select bit. The decision and syndromes of each component codeword to which the select bit belongs are updated based on the compare operation.

公开(公告)号：US10707899B2

公开(公告)日：2020-07-07

申请号：US15917222

申请日：2018-03-09

Applicant: SK Hynix Inc.

Inventor： Aman Bhatia ,  Naveen Kumar ,  Chenrong Xiong ,  Fan Zhang ,  Xuanxuan Lu ,  Yu Cai

IPC: H03M13/11 ,  G11C29/42 ,  G06F11/10

Abstract: Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.

公开(公告)号：US20200210286A1

公开(公告)日：2020-07-02

申请号：US16717857

申请日：2019-12-17

Applicant: SK hynix Inc.

Inventor： Naveen Kumar ,  Chenrong Xiong ,  Aman Bhatia ,  Yu Cai ,  Fan Zhang

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/45

Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

公开(公告)号：US10484020B2

公开(公告)日：2019-11-19

申请号：US15668565

申请日：2017-08-03

Applicant: SK Hynix Inc.

Inventor： Aman Bhatia ,  Yi-Min Lin ,  Naveen Kumar ,  Johnson Yen

IPC: H03M13/29 ,  H03M13/37 ,  H03M13/39 ,  H03M13/15

Abstract: A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, and each data block having a number of data bits. The decoding apparatus is configured to decode, in parallel, a first codeword with one or more other codewords to determine error information associated with each codeword. For errors in a common data block shared between two codewords being decoded in parallel, the error information includes a data block identifier and associated error bit patterns. Further, the decoding apparatus is configured to update the codewords based on the error information.

公开(公告)号：US10432363B2

公开(公告)日：2019-10-01

申请号：US15674134

申请日：2017-08-10

Applicant: SK hynix Inc.

Inventor： Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin

IPC: G11C29/00 ,  H04L1/20 ,  G06F11/07 ,  G11C29/50 ,  G11C16/34 ,  G11C11/56 ,  G11C29/02 ,  G11C29/52 ,  G06F11/10 ,  G11C29/56 ,  G11C16/04 ,  G11C29/04

Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

公开(公告)号：US20190212940A1

公开(公告)日：2019-07-11

申请号：US16136989

申请日：2018-09-20

Applicant: SK Hynix Inc.

Inventor： Yu Cai ,  Naveen Kumar ,  Aman Bhatia ,  Fan Zhang

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F3/0649 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/076 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Techniques for profiling storage blocks in non-transitory memory (e.g., flash memory dies) to determine their retention capability, and assigning them with labels based on retention, are described. A superblock (SB) can be formed from physical blocks with the same labels located in different dies. The disclosed system and methods improve storage efficiency when the update frequency of stored data is non-uniform, as is typically the case. Moreover, the disclosed embodiments improve the reliability of solid state drives (SSDs), as well as reduce data refresh frequency and write amplification due to periodic refresh. A storage system can comprise a controller configured to obtain expected retention times for a plurality of storage blocks. The controller can partition the blocks into superblocks based on the retention times. A respective superblock is associated with a superblock retention time range, and contains blocks having expected retention times within the retention time range.

公开(公告)号：US10348335B2

公开(公告)日：2019-07-09

申请号：US15156088

申请日：2016-05-16

Applicant: SK hynix Inc.

Inventor： Aman Bhatia ,  Naveen Kumar ,  Yi-Min Lin ,  Lingqi Zeng

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29

Abstract: Systems may include a memory storage suitable for storing data, an encoder suitable for encoding data into codewords arranged in an array of a number of rows and a number of columns, and a decoder suitable for receiving the encoded codewords, decoding the encoded codewords, and detecting miscorrections in the decoding.

公开(公告)号：US10326473B2

公开(公告)日：2019-06-18

申请号：US15487231

申请日：2017-04-13

Applicant: SK Hynix Inc.

Inventor： Aman Bhatia ,  June Lee ,  Chenrong Xiong ,  Naveen Kumar ,  Fan Zhang ,  Yu Cai

IPC: G11C29/00 ,  H03M13/11 ,  G06F11/10 ,  G06F11/30 ,  G06F11/34 ,  G11C11/56 ,  G11C16/08 ,  H03M13/00

Abstract: Techniques for processing bits associated with an “N” multiple level cell NAND flash memory, such as a QLC NAND flash memory, are described. In an example, a system generates a symbol based on the bits. The symbol corresponds to at least two bits. The system encodes the symbol in a non-binary codeword and stores the non-binary codeword in the “N” multiple level cell NAND flash memory based on a mapping between symbols and voltage levels of the “N” multiple level cell NAND flash memory. The system initializes a non-binary decoding procedure based on asymmetric crossover probabilities between the voltage levels. The asymmetric crossover probabilities are defined based on the mapping between the symbols and the voltage level. The system decodes the non-binary codeword based on the non-binary decoding procedure.