公开(公告)号：US09054697B2

公开(公告)日：2015-06-09

申请号：US13890802

申请日：2013-05-09

Applicant: SK hynix Inc.

Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

IPC: H03K19/23 ,  H03K19/003 ,  H03K19/08

CPC classification number: H03K19/0813 ,  H03K19/23

Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

Abstract translation: 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段

公开(公告)号：US09018991B2

公开(公告)日：2015-04-28

申请号：US14106817

申请日：2013-12-15

Applicant: SK Hynix Inc. ,  Industry-University Cooperation Foundation Hanyang University

Inventor： Hae-Rang Choi ,  Yong-Ju Kim ,  Oh-Kyong Kwon ,  Kang-Sub Kwak ,  Jun-Yong Song ,  Hyeon-Cheon Seol

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03L7/0807 ,  H04L7/0337 ,  H04L7/044

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract translation: 数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号 适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。