-
公开(公告)号：US09054697B2
公开(公告)日：2015-06-09
申请号：US13890802
申请日：2013-05-09
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Oh-Kyong Kwon , Kang-Sub Kwak , Jun-Yong Song , Hyeon-Cheon Seol
IPC: H03K19/23 , H03K19/003 , H03K19/08
CPC classification number: H03K19/0813 , H03K19/23
Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.
Abstract translation: 多数决定电路包括：多数决定单元，被配置为将第一数据与第二数据进行比较，以确定第一数据和第二数据之一是否具有更多具有第一逻辑值的位; 以及偏移应用单元，被配置为控制多数决定单元，使得多数决定单元在第一数据中具有第一逻辑值的比特数等于具有第一逻辑值的比特数在 第二数据，如果偏移量是第一相位中的第一设定值，则第一数据具有具有第一逻辑值的更多位，并且如果偏移量是第二设定值，则判定第二数据具有第一逻辑值的更多位 第二阶段
-
2.发明授权公开(公告)号：US08717217B2
公开(公告)日：2014-05-06
申请号：US13718653
申请日：2012-12-18
Applicant: SK hynix Inc.
Inventor： Ja-Seung Gou , Oh-Kyong Kwon , Min-Seok Shin , Min-Kyu Kim
IPC: H03M1/12
Abstract: An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1st to Nth capacitors having one ends connected to the input node, respectively; and 1st to N−1th voltage selection units corresponds to the 2nd to Nth capacitors, respectively and applies one of a voltages of a 1st node, a 2nd node, and the comparison voltage to the other ends of the corresponding capacitors. An input signal is sampled to the input node, the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert a part of the input signal into a 1st digital signal, and the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert the remaining part of the input signal into a 2nd digital signal.
Abstract translation: 模数转换器包括比较单元，其输出通过将输入节点的电压与比较电压进行比较而获得的结果; 分别具有一端连接到输入节点的第1至第N电容器; 第1〜第N电压选择单元分别对应于第2〜第N电容器，并将相应的电容器的另一端施加第1节点，第2节点和第2节点的电压中的一个。 输入信号被采样到输入节点，第1到第N-1个电压选择单元选择2个节点中的一个电压，并将一部分输入信号转换为第1数字信号，第1至第N-1个电压 选择单元选择2个节点的一个电压，并将输入信号的剩余部分转换为第二个数字信号。
-
Patent Agency Ranking
3.发明授权SAR analog-to-digital converting apparatus and operating method thereof and CMOS image sensor including the same 有权SAR模数转换装置及其操作方法和包括其的CMOS图像传感器公开(公告)号：US09231610B2
公开(公告)日：2016-01-05
申请号：US14293736
申请日：2014-06-02
Inventor： Ja-Seung Gou , Min-Kyu Kim , Oh-Kyong Kwon
Abstract: A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N−1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N−2 bit analog-to-digital conversion result by combining converted upper N−1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.
Abstract translation: 逐次近似寄存器（SAR）模数转换装置包括：一个参考电压供应单元，适用于根据要转换的像素输出信号的位提供不同的参考电压; N位SAR模数转换单元适合 用于通过选择性地使用从参考电压提供单元提供的参考电压顺序地转换像素输出信号的上N-1位和低N位，其中N是自然数，以及纠错单元适合于计算误差校正值 基于低N位的转换结果之间的差异，并通过组合转换的上N-1位和转换的低N位来输出2N-2位模数转换结果，并使用 组合中的纠错值。
-
公开(公告)号：US09018991B2
公开(公告)日：2015-04-28
申请号：US14106817
申请日：2013-12-15
Inventor： Hae-Rang Choi , Yong-Ju Kim , Oh-Kyong Kwon , Kang-Sub Kwak , Jun-Yong Song , Hyeon-Cheon Seol
CPC classification number: H03L7/0807 , H04L7/0337 , H04L7/044
Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
Abstract translation: 数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号 适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。
-
5.发明授权Analog-to-digital conversion circuit, analog-to-digital conversion method, and image sensor 有权模数转换电路，模数转换方式和图像传感器公开(公告)号：US08922403B2
公开(公告)日：2014-12-30
申请号：US14051102
申请日：2013-10-10
Inventor： Ja-Seung Gou , Oh-Kyong Kwon , Min-Seok Shin , Min-Kyu Kim
CPC classification number: H03M1/0607 , H03M1/007 , H03M1/56 , H03M1/58
Abstract: An analog-to-digital conversion circuit includes an analog-to-digital conversion unit configured to analog-to-digital convert an input voltage and generate a digital signal, a resolution control unit configured to: set a resolution of the analog-to-digital conversion unit to N (N is the natural number) bits, in a case where the input voltage is smaller than a first voltage, and set the resolution of the analog-to-digital conversion unit to N−M (1≦M
Abstract translation: 模拟数字转换电路包括被配置为模数转换输入电压并产生数字信号的模数转换单元，分辨率控制单元，被配置为：将模拟 - 在输入电压小于第一电压的情况下，将数字转换单元设置为N（N为自然数）位，并将模数转换单元的分辨率设置为N-M（1＆nl; M＆ 在输入电压大于第一电压的情况下，N，M是自然数）比特;以及信号校正单元，被配置为：在第一电压和第二电压之间产生校正的数字信号，基于边界值和数字信号， 数字信号的值大于边界值，并且输入电压小于第一电压。
-
公开(公告)号：US09667899B2
公开(公告)日：2017-05-30
申请号：US14543835
申请日：2014-11-17
Inventor： Ja-Seung Gou , Oh-Kyong Kwon , Min-Kyu Kim
Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.
-
公开(公告)号：US09490853B2
公开(公告)日：2016-11-08
申请号：US14856409
申请日：2015-09-16
Inventor： Kang-Sub Kwak , Jong-Hyun Ra , Oh-Kyong Kwon , Hae-Rang Choi , Yong-Ju Kim
Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.
Abstract translation: 数据发射机可以包括发射机电路和校准控制器。 发射机电路被配置为通过信道耦合到接收机，并且被配置为基于输入信号向信道提供输出信号，并根据偏置信号调整输出阻抗值。 校准控制器被配置为通过在校准操作期间将发射机电路的输出信号与参考信号进行比较来调整偏置信号。
-
-
-
-
-
-
Search Results
7
records
(took 0.012 seconds)
