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    Signal converter
    1.
    发明授权
    Signal converter 有权
    信号转换器

    公开(公告)号：US09312872B1

    公开(公告)日：2016-04-12

    申请号：US14845023

    申请日：2015-09-03

    Applicant: SK hynix Inc.

    Inventor： Ji-Hwan Kim

    IPC: H03M1/50 ,  H03M1/00 ,  H03M1/60 ,  G04F10/00

    CPC classification number: G01R29/02 ,  G04F10/005 ,  H03M1/50 ,  H03M1/60

    Abstract: A signal converter may include: a clock generation unit suitable for generating a counting clock signal having a given period value; a signal dividing unit suitable for dividing an input signal having time information by a preset division value correlated with the given period value; and a counting unit suitable for generating a counting value by counting an output signal of the signal dividing unit in response to the counting clock signal.

    Abstract translation: 信号转换器可以包括：适于产生具有给定周期值的计数时钟信号的时钟产生单元; 信号分割单元，适于将具有时间信息的输入信号除以与给定周期值相关的预设分频值; 以及计数单元，适于通过响应于计数时钟信号对信号分割单元的输出信号进行计数来产生计数值。

    Integrated circuit
    2.
    发明授权
    Integrated circuit 有权

    公开(公告)号：US10991400B2

    公开(公告)日：2021-04-27

    申请号：US16221757

    申请日：2018-12-17

    Applicant: SK hynix Inc.

    Inventor： Heat-Bit Park ,  Ji-Hwan Kim ,  Dong-Uk Lee

    IPC: G11C7/10

    Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

    Semiconductor device including clock generation circuit
    4.
    发明授权
    Semiconductor device including clock generation circuit 有权

    公开(公告)号：US11038497B2

    公开(公告)日：2021-06-15

    申请号：US16829834

    申请日：2020-03-25

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Ji-Hwan Kim

    IPC: G06F1/04 ,  H03K5/135 ,  H03K21/38 ,  G01R31/317 ,  H03K23/00 ,  G06F1/10 ,  H03K5/00

    Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

    Stacked semiconductor device
    5.
    发明授权
    Stacked semiconductor device 有权

    公开(公告)号：US10074579B1

    公开(公告)日：2018-09-11

    申请号：US15709785

    申请日：2017-09-20

    Applicant: SK hynix Inc.

    Inventor： Ji-Hwan Kim ,  Dong-Uk Lee

    IPC: H01L21/66 ,  H01L25/065 ,  G01R31/28 ,  G01R31/02

    Abstract: A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated channels through a plurality of through-electrodes. Each of the core dies may include: a through-electrode scan unit enabled according to allocated channel information, and suitable for performing a down scan of transmitting a signal downward through through-electrodes connected in a column direction among the through-electrodes and an up scan of transmitting a signal upward through the through-electrodes connected in the column direction; and a defect detection unit suitable for detecting whether the through-electrodes have a defect, based on the down scan and the up scan.

    Memory device including grouped page buffers and read operation method thereof
    7.
    发明授权
    Memory device including grouped page buffers and read operation method thereof 有权

    公开(公告)号：US11152072B2

    公开(公告)日：2021-10-19

    申请号：US16662900

    申请日：2019-10-24

    Applicant: SK hynix Inc.

    Inventor： Jung-Mi Ko ,  Ji-Hwan Kim ,  Seong-Je Park

    IPC: G11C16/26 ,  G06F12/0882 ,  G06F12/02 ,  G11C16/08 ,  G06F3/06 ,  G11C16/24

    Abstract: A memory device includes a memory cell array including a plurality of memory cells, a plurality of first even page buffers suitable for reading data from first even-numbered memory cells among the plurality of memory cells, and storing the read data, a plurality of first odd page buffers suitable for reading data from first odd-numbered memory cells among the plurality of memory cells, and storing the read data, and a plurality of first cache buffers corresponding to the first even page buffers, suitable for storing data received through a first common node from the first even page buffers, and a plurality of second cache buffers corresponding to the first odd page buffers, and suitable for storing data received through the first common node from the first odd page buffers.

    Integrated circuit chip
    8.
    发明授权
    Integrated circuit chip 有权

    公开(公告)号：US10748601B2

    公开(公告)日：2020-08-18

    申请号：US16127845

    申请日：2018-09-11

    Applicant: SK hynix Inc.

    Inventor： Ji-Hwan Kim ,  Heat-Bit Park

    IPC: G11C7/10 ,  G11C11/4096 ,  G11C5/06 ,  G11C29/36 ,  G11C29/02 ,  G11C5/02 ,  G11C29/12

    Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.

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