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    Clock monitoring circuit
    2.
    发明授权
    Clock monitoring circuit 有权

    公开(公告)号：US10410701B2

    公开(公告)日：2019-09-10

    申请号：US16159930

    申请日：2018-10-15

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Young-Jae Choi

    IPC: G06F1/08 ,  G11C7/22 ,  G06F1/14 ,  G06F1/12 ,  G06F1/10

    Abstract: A clock monitoring circuit includes: a sampling circuit suitable for sampling a monitoring target clock in synchronization with a sampling clock; a first counter circuit suitable for counting the number of times that the sampling circuit samples the monitoring target clock at a predetermined level; and a second counter circuit suitable for counting the number of times that the sampling circuit performs sampling.

    Memory device and memory system including the same
    4.
    发明授权
    Memory device and memory system including the same 有权

    公开(公告)号：US10678716B2

    公开(公告)日：2020-06-09

    申请号：US16234895

    申请日：2018-12-28

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Seok-Woo Choi ,  Young-Jae Choi

    IPC: G06F13/16 ,  H01L25/18 ,  H01L25/065 ,  G06F13/28

    Abstract: A memory device includes: a plurality of first control signal interfaces respectively corresponding to a plurality of channels, and suitable for receiving control signals from a host; a plurality of first data interfaces respectively corresponding to the plurality of channels, and suitable for exchanging data and data strobe signals with the host; a second control signal interface suitable for receiving control signals through a selected one of the first control signal interfaces and a selected one of the channels and outputting the received control signals, in a monitoring mode; and a second data interface suitable for receiving a part of the data and data strobe signals exchanged through a selected one of the first data interfaces and the selected channel, and outputting the received part of the data and data strobe signals, in the monitoring mode.

    Memory device
    5.
    发明授权
    Memory device 有权

    公开(公告)号：US10593378B2

    公开(公告)日：2020-03-17

    申请号：US16152549

    申请日：2018-10-05

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Young-Jae Choi

    IPC: G11C7/10 ,  H01L25/18 ,  H01L25/065 ,  G11C5/06 ,  G11C5/04

    Abstract: A memory device includes: a plurality of data pads; a data distribution circuit suitable for distributing data received through some data pads of the plurality of data pads to a first data bus, and distributing data received through the other data pads to a second data bus, in a first mode; a first channel region suitable for storing data obtained by copying the data of the first data bus at a predetermined ratio of 1:N where N is an integer equal to or more than 2; and a second channel region suitable for storing data obtained by copying the data of the second data bus at the predetermined ratio of 1:N.

    Semiconductor device including clock generation circuit
    6.
    发明授权
    Semiconductor device including clock generation circuit 有权

    公开(公告)号：US11038497B2

    公开(公告)日：2021-06-15

    申请号：US16829834

    申请日：2020-03-25

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Ji-Hwan Kim

    IPC: G06F1/04 ,  H03K5/135 ,  H03K21/38 ,  G01R31/317 ,  H03K23/00 ,  G06F1/10 ,  H03K5/00

    Abstract: A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

    Stacked memory device and memory system including the same
    7.
    发明授权
    Stacked memory device and memory system including the same 有权

    公开(公告)号：US11037608B2

    公开(公告)日：2021-06-15

    申请号：US16677289

    申请日：2019-11-07

    Applicant: SK hynix Inc.

    Inventor： Myeong-Jae Park ,  Chun-Seok Jeong

    IPC: G11C5/14 ,  G11C7/10 ,  H01L23/00 ,  G11C7/22 ,  H01L25/065

    Abstract: A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.

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