公开(公告)号：US09196607B2

公开(公告)日：2015-11-24

申请号：US14082441

申请日：2013-11-18

Applicant: SK hynix Inc.

Inventor： Jin Ho Bae ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/92135 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.

Abstract translation: 堆叠封装包括具有连接端子的基板和在基板上的第一芯片。 第一芯片在其边缘上具有第一连接器。 第二芯片堆叠在第一芯片上以暴露第一连接器的外部部分。 第二芯片在其边缘上具有第二连接器。 连接构件将第一连接器的暴露的外部部分连接到连接端子。 将第一连接器的暴露的外部部分连接到第二连接器的侧壁互连器。 侧壁互连器从第一连接器的暴露的外部部分延伸到第二芯片的侧壁以覆盖第二连接器。

公开(公告)号：US09972568B2

公开(公告)日：2018-05-15

申请号：US15718319

申请日：2017-09-28

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae ,  Chan Woo Jeong

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/4985 ,  H01L23/293 ,  H01L23/298 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32238

Abstract: A semiconductor package includes a molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. The molding member includes an extendible material which includes a first part having a warped shape, a second part extending from one end of the first part to be flat, and a third part extending from the other end of the first part to be flat, where first surfaces of the connectors are exposed at a surface of the molding member and second surfaces of the connectors are coupled to the chip.

公开(公告)号：US20170064832A1

公开(公告)日：2017-03-02

申请号：US14989921

申请日：2016-01-07

Applicant: SK hynix Inc.

Inventor： Seung Yeop Lee ,  Joo Hyun Kang ,  Jong Hoon Kim ,  Han Jun Bae

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/028 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/14 ,  H05K1/147 ,  H05K2201/0385 ,  H05K2201/05 ,  H05K2201/058 ,  H01L2924/00012

Abstract: A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.

Abstract translation: 柔性器件包括第一导电图案，第二导电图案和介电层。 第一导电图案包括第一滑动接触部分和第一延伸部分。 第二导电图案包括与第一滑动接触部分重叠的第二滑动接触部分，并且第二导电图案包括第二延伸部分。 第二滑动接触部分与第一滑动接触部分接触并可在第一滑动接触部分上移动以进行滑动。 第一和第二导电图案嵌入在介电层中。

公开(公告)号：US09543384B2

公开(公告)日：2017-01-10

申请号：US14850385

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Han Jun Bae ,  Won Duck Jung

IPC: H01L23/495 ,  H01L25/065 ,  H01L29/06 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L29/0657 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Abstract translation: 半导体器件包括衬底，设置在衬底的表面上的弹性缓冲层，布置在弹性缓冲层的第一表面上的布线图案，以及布置在弹性缓冲层的背离弹性缓冲层的第二表面上的半导体芯片 弹性缓冲层的第一表面。 半导体芯片包括形成在面向弹性缓冲层的表面上的沟槽。 互连构件被设置为将弹性缓冲层电连接到衬底。 每个互连构件的一端电连接到一个布线图案，另一端电连接到基板。

公开(公告)号：US11270958B2

公开(公告)日：2022-03-08

申请号：US16991683

申请日：2020-08-12

Applicant: SK hynix Inc.

Inventor： Ju Il Eom ,  Jin Kyoung Park ,  Han Jun Bae

IPC: H01L23/64 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

公开(公告)号：US09888567B2

公开(公告)日：2018-02-06

申请号：US14989921

申请日：2016-01-07

Applicant: SK hynix Inc.

Inventor： Seung Yeop Lee ,  Joo Hyun Kang ,  Jong Hoon Kim ,  Han Jun Bae

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H05K1/14

CPC classification number: H05K1/028 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5387 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/14 ,  H05K1/147 ,  H05K2201/0385 ,  H05K2201/05 ,  H05K2201/058 ,  H01L2924/00012

Abstract: A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.

公开(公告)号：US09847285B1

公开(公告)日：2017-12-19

申请号：US15435951

申请日：2017-02-17

Applicant: SK hynix Inc.

Inventor： Ki Jun Sung ,  Jong Hoon Kim ,  Han Jun Bae

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/18161

Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

公开(公告)号：US09806015B1

公开(公告)日：2017-10-31

申请号：US15419267

申请日：2017-01-30

Applicant: SK hynix Inc.

Inventor： Ki Jun Sung ,  Jong Hoon Kim ,  Han Jun Bae

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06572 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16251 ,  H01L2924/18161

Abstract: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

公开(公告)号：US09214410B2

公开(公告)日：2015-12-15

申请号：US14245618

申请日：2014-04-04

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 提供堆栈包。 堆叠包装包括第一芯片和第二芯片。 第一芯片包括第一芯片体，穿过第一芯片体的第一穿透电极和设置在第一芯片主体的底表面上的绝缘层。 第二芯片包括设置在第二芯片主体的顶表面上的第二芯片体和凸块。 第一和第二芯片垂直堆叠，使得凸块穿透绝缘层以刺穿第一通孔，第二芯片体的顶表面直接接触绝缘层。 还提供了相关的制造方法，电子系统和存储卡。

公开(公告)号：US11309303B2

公开(公告)日：2022-04-19

申请号：US17156239

申请日：2021-01-22

Applicant: SK hynix Inc.

Inventor： Ju Il Eom ,  Han Jun Bae ,  Seung Yeop Lee

IPC: H01L25/18 ,  H01L23/64 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.