-
公开(公告)号：US20240007085A1
公开(公告)日：2024-01-04
申请号：US18106915
申请日：2023-02-07
Applicant: SK hynix Inc.
Inventor： Dae Ho YANG , Min Su KIM , Kwan Su SHON , Keun Seon AHN , Soon Sung AN , Su Han LEE , Jae Hoon JUNG , Kyeong Min CHAE , Jae Hyeong HONG , Jun Sun HWANG
CPC classification number: H03K3/017 , H03K5/1565 , H03K5/135 , H03K5/05
Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.
-
公开(公告)号：US20240161793A1
公开(公告)日：2024-05-16
申请号：US18115999
申请日：2023-03-01
Applicant: SK hynix Inc.
Inventor： Heon Ki KIM , Kyeong Min CHAE
CPC classification number: G11C7/1063 , G11C7/106 , G11C7/1066 , G11C7/222
Abstract: A pipe register includes: a plurality of register units configured to output data in response to control signals; and a pipe control circuit configured to generate a reference timing signal by dividing a clock signal, the clock signal activated during an activation time of a read enable signal, and generate the control signals based on the read enable signal and the reference timing signal.
-
公开(公告)号：US20210271605A1
公开(公告)日：2021-09-02
申请号：US16994180
申请日：2020-08-14
Applicant: SK hynix Inc.
Inventor： Jin Ha HWANG , Kyeong Min CHAE , Jun Sun HWANG
IPC: G06F12/0891 , G11C7/10
Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.
-
4.发明申请公开(公告)号：US20160111136A1
公开(公告)日：2016-04-21
申请号：US14586362
申请日：2014-12-30
Applicant: SK hynix Inc.
Inventor： Kyeong Min CHAE
CPC classification number: G11C8/10 , G11C8/06 , G11C8/18 , G11C29/702
Abstract: An address decoding circuit may include a main address processing block configured to latch a main address, and output a latched main address. The address decoding circuit may include a repair block configured to determine whether the main address corresponds to a failed region, and output a repair address and a repair signal according to a determination result. The address decoding circuit may include a synchronization block configured to synchronize the latched main address, the repair address and the repair signal with a synchronization signal, and output a synchronized main address, a synchronized repair address and a synchronized repair signal. The address decoding circuit may include a decoder configured to decode any one of the synchronized main address and the synchronized repair address in response to a decoding signal.
Abstract translation: 地址解码电路可以包括主地址处理块，其被配置为锁存主地址，并输出锁存的主地址。 地址解码电路可以包括修复块，其被配置为确定主地址是否对应于故障区域，并且根据确定结果输出修复地址和修复信号。 地址解码电路可以包括同步块，其被配置为使锁存的主地址，修复地址和修复信号与同步信号同步，并输出同步的主地址，同步的修复地址和同步修复信号。 地址解码电路可以包括解码器，其被配置为响应于解码信号来解码同步主地址和同步修复地址中的任何一个。
-
公开(公告)号：US20220253090A1
公开(公告)日：2022-08-11
申请号：US17365252
申请日：2021-07-01
Applicant: SK hynix Inc.
Inventor： Kyeong Min CHAE
Abstract: A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.
-
Patent Agency Ranking
公开(公告)号：US20200057574A1
公开(公告)日：2020-02-20
申请号：US16380361
申请日：2019-04-10
Applicant: SK hynix Inc.
Inventor： KangYoul LEE , Kyeong Min CHAE
IPC: G06F3/06
Abstract: A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.
-
公开(公告)号：US20180004429A1
公开(公告)日：2018-01-04
申请号：US15395698
申请日：2016-12-30
Applicant: SK hynix Inc.
Inventor： Kyeong Min CHAE
CPC classification number: G06F3/0611 , G06F3/0656 , G06F3/068 , G11C7/10 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C7/14 , G11C7/222 , G11C8/10 , G11C16/0483 , G11C16/26 , G11C16/32
Abstract: A memory device may include a data output controller for generating a first clock signal and a second clock signal in response to a read enable clock signal, a page buffer for storing data, and outputting the data to the data output controller in synchronization with the first clock signal, and a data output buffer for receiving the data from the page buffer and outputting the received data to the external device in synchronization with the second clock signal. The first clock signal is generated in response to a data output delay control signal, the second clock signal is generated irrespective of the data output delay control signal.
-
公开(公告)号：US20250124957A1
公开(公告)日：2025-04-17
申请号：US18436021
申请日：2024-02-08
Applicant: SK hynix Inc.
Inventor： Young Seung YOO , Ji Seong MUN , Hyeon Cheon SEOL , Sung Hwa OK , Sung Wook CHO , Kyeong Min CHAE , Hyun Kyu KANG , Won Keun SONG
IPC: G11C7/10
Abstract: A pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. Plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. Plural second switches are configured to output the plural data entries stored in the plural second inverter latches.
-
公开(公告)号：US20200027510A1
公开(公告)日：2020-01-23
申请号：US16299590
申请日：2019-03-12
Applicant: SK hynix Inc.
Inventor： Sang Hwan KIM , Min Su KIM , Kyeong Min CHAE
Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.
-
公开(公告)号：US20180336936A1
公开(公告)日：2018-11-22
申请号：US15850713
申请日：2017-12-21
Applicant: SK hynix Inc.
Inventor： Kyeong Min CHAE
CPC classification number: G11C7/1057 , G11C7/1039 , G11C7/106 , G11C7/1063 , G11C7/1066 , G11C7/1069 , G11C7/222 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/26 , G11C16/32 , G11C2211/5642
Abstract: A memory device includes a page buffer group configured to read normal data stored in a memory cell array, a control logic configured to store logic data, and a pipe latch control unit configured to latch the normal data outputted from the page buffer group in synchronization with a read enable pipe signal and latch the logic data outputted from the control logic in synchronization with the read enable pipe signal.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.013 seconds)
