公开(公告)号：US20210117349A1

公开(公告)日：2021-04-22

申请号：US16855566

申请日：2020-04-22

Applicant: SK hynix Inc.

Inventor： Kyu Young KIM ,  Dae Han KWON ,  Ha Jun JEONG

IPC: G06F13/20 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

公开(公告)号：US20250157522A1

公开(公告)日：2025-05-15

申请号：US18610896

申请日：2024-03-20

Applicant: SK hynix Inc.

Inventor： Jung Taek YOU ,  Han Byeol KWON ,  Kyu Young KIM

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor device includes a clock division circuit configured to generate division clocks from a clock signal, based on a division enable signal that is activated based on a chip selection signal, and a valid time determination circuit configured to generate a valid signal for setting a generation time of a command, based on the chip selection signal and the division clocks.

公开(公告)号：US20220077862A1

公开(公告)日：2022-03-10

申请号：US17159952

申请日：2021-01-27

Applicant: SK hynix Inc.

Inventor： Gi Moon HONG ,  Dae Han KWON ,  Kyu Young KIM

IPC: H03L7/081 ,  H03L7/085 ,  G11C7/22 ,  G06F3/06 ,  G06F1/08

Abstract: A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.

公开(公告)号：US20150124549A1

公开(公告)日：2015-05-07

申请号：US14244733

申请日：2014-04-03

Applicant: SK hynix Inc.

Inventor： Kyu Young KIM

IPC: H03K5/153 ,  G11C8/18

CPC classification number: H03K5/153 ,  G11C5/066 ,  G11C7/1087 ,  G11C8/18

Abstract: The semiconductor device includes a pulse width comparator suitable for generating an internal pulse signal having the same pulse width as an output pulse signal whose pulse width is controlled by first and second control signals during a predetermined period and suitable for generating first and second digital signals and a comparison pulse signal from the internal pulse signal according to a delay time which is set by the first and second control signals, an output pulse signal generator suitable for retarding the comparison pulse signal by the delay time determined by first and second control signals to generate the output pulse signal, and a control signal generator suitable for generating the first and second control signals which are sequentially enabled in response to pulses of the output pulse signal.

Abstract translation: 该半导体器件包括：脉冲宽度比较器，适合于产生与脉冲宽度在预定时间段内由第一和第二控制信号控制并且适于产生第一和第二数字信号的输出脉冲信号具有相同脉冲宽度的内部脉冲信号;以及 来自内部脉冲信号的比较脉冲信号根据由第一和第二控制信号设置的延迟时间，输出脉冲信号发生器适合于将比较脉冲信号延迟由第一和第二控制信号确定的延迟时间，以产生 输出脉冲信号和适于产生响应于输出脉冲信号的脉冲被依次使能的第一和第二控制信号的控制信号发生器。

公开(公告)号：US20180331686A1

公开(公告)日：2018-11-15

申请号：US15802216

申请日：2017-11-02

Applicant: SK hynix Inc.

Inventor： Kyu Young KIM

IPC: H03L7/085 ,  G06F1/08 ,  H03K5/135

CPC classification number: H03L7/085 ,  G06F1/08 ,  H03K5/135

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a clock generation circuit. The clock generation circuit may be configured to receive data clock signals and generate internal clock signals in both a first and second operation mode.

公开(公告)号：US20170179938A1

公开(公告)日：2017-06-22

申请号：US15157564

申请日：2016-05-18

Applicant: SK hynix Inc.

Inventor： Myeong Jae PARK ,  Kyung Hoon KIM ,  Kyu Young KIM ,  Woo Yeol SHIN

IPC: H03K5/15 ,  G01R23/02 ,  G01R25/08 ,  H03K5/24 ,  H02M3/07

CPC classification number: H03K5/1506 ,  G01R23/02 ,  G01R25/08 ,  H02M3/07 ,  H03K5/24 ,  H03K19/21

Abstract: A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.