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    PERIOD SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    1.
    发明申请
    PERIOD SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权
    周期性信号发生电路和包括它的半导体系统

    公开(公告)号：US20170054436A1

    公开(公告)日：2017-02-23

    申请号：US14878922

    申请日：2015-10-08

    Applicant: SK hynix Inc.

    Inventor： Myeong Jae PARK ,  Kyung Hoon KIM ,  Woo Yeol SHIN ,  Han Kyu CHI

    IPC: H03K5/01 ,  H03K3/037

    CPC classification number: H03K3/0315 ,  H03K3/014 ,  H03K5/13 ,  H03K5/19

    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.

    Abstract translation: 半导体系统可以包括被配置为输出命令和接收数据的第一半导体器件。 半导体系统可以包括：第二半导体器件，被配置为产生周期信号，响应于该命令周期性地切换的周期信号，响应周期信号输出数据，并且如果周期信号是 在预定部分期间不切换。

    INTERPOSER FOR INSPECTING SEMICONDUCTOR CHIP
    3.
    发明申请
    INTERPOSER FOR INSPECTING SEMICONDUCTOR CHIP 有权
    用于检查半导体芯片的间隔器

    公开(公告)号：US20160305983A1

    公开(公告)日：2016-10-20

    申请号：US15090907

    申请日：2016-04-05

    Applicant: SK hynix Inc.

    Inventor： Jae Hwan SEO ,  Woo Yeol SHIN

    IPC: G01R1/073 ,  G01R31/26 ,  H01L23/498

    CPC classification number: G01R1/07378 ,  G01R1/0483 ,  H01L22/00 ,  H01L23/49811 ,  H01L23/49827

    Abstract: An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.

    Abstract translation: 公开了一种用于检查半导体芯片的可靠性的插入件。 用于检查的插入件包括：设置在第一表面的有源区域中的至少一个有源焊盘，并且包括：焊盘，其中接收（输入）数据和用于测试检测目标芯片的控制信号并输出​​（输出） 主动模式; 以及用于在活动模式期间接收操作检查目标芯片和插入器所需的电源电压的焊盘; 设置在所述第一表面的无源区域中的至少一个无源焊盘，并且包括：在被动模式期间接收用于测试所述检查目标芯片的数据的焊盘以及在所述第一表面期间操作所述检测目标芯片和所述插入器所需的电源电压 被动模式; 以及设置在面向所述第一表面的第二表面上的至少一个凸块焊盘，并且耦合到所述检查目标芯片。

    SEMICONDUCTOR SYSTEM
    4.
    发明申请
    SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20190139589A1

    公开(公告)日：2019-05-09

    申请号：US16238377

    申请日：2019-01-02

    Applicant: SK hynix Inc.

    Inventor： Keun Soo SONG ,  Woo Yeol SHIN

    IPC: G11C8/18 ,  G11C8/06 ,  G06F13/42 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A semiconductor system may include a controller configured to provide a command clock and a control signal to a semiconductor memory device, and the semiconductor memory device configured to transmit/receive external data and a plurality of data clocks to/from the controller, wherein the plurality of data clocks comprise a first read data strobe signal and a second read data strobe signal, and the semiconductor memory device transmits both of the first read data strobe signal and the second read data strobe signal to the controller or transmits one of the first read data strobe signal and the second read data strobe signal to the controller, based on an operation select signal.

    SEMICONDUCTOR SYSTEM
    6.
    发明申请
    SEMICONDUCTOR SYSTEM 有权

    公开(公告)号：US20170162245A1

    公开(公告)日：2017-06-08

    申请号：US15203937

    申请日：2016-07-07

    Applicant: SK hynix Inc.

    Inventor： Keun Soo SONG ,  Woo Yeol SHIN

    IPC: G11C8/18 ,  G11C8/06

    CPC classification number: G11C8/18 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.

    SEMICONDUCTOR SYSTEM
    7.
    发明申请
    SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20180342275A1

    公开(公告)日：2018-11-29

    申请号：US16054777

    申请日：2018-08-03

    Applicant: SK hynix Inc.

    Inventor： Keun Soo SONG ,  Woo Yeol SHIN

    IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G06F13/42 ,  G11C8/06

    CPC classification number: G11C8/18 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A semiconductor system may include a controller configured to provide a first external clock and a control signal to a semiconductor device, and the semiconductor device configured to transmit/receive external data and a plurality of second external clocks to/from the controller, wherein the plurality of second external clocks comprise a third primary external clock and a third secondary external clock, and the semiconductor device transmits both of the third primary external clock and the third secondary external clock to the controller or to transmits one of the third primary external clock and the third secondary external clock to the controller, based on an operation select signal.

    SEMICONDUCTOR SYSTEM
    8.
    发明申请
    SEMICONDUCTOR SYSTEM 审中-公开

    公开(公告)号：US20180151208A1

    公开(公告)日：2018-05-31

    申请号：US15882808

    申请日：2018-01-29

    Applicant: SK hynix Inc.

    Inventor： Keun Soo SONG ,  Woo Yeol SHIN

    IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G06F13/42 ,  G11C7/10

    CPC classification number: G11C8/18 ,  G06F13/4234 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/06

    Abstract: A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a first external clock. The controller may be configured to transmit a second external clock and receive a third external clock for receiving/transmitting external data. The semiconductor memory device may be configured to synchronize and receive the external address and the external command with the first external clock. The semiconductor memory device may be configured to synchronize and receive the external data with the second external clock. The semiconductor memory device may be configured to transmit the external data and the third external clock to the controller.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权
    半导体器件和包括其的半导体系统

    公开(公告)号：US20160064101A1

    公开(公告)日：2016-03-03

    申请号：US14568229

    申请日：2014-12-12

    Applicant: SK hynix Inc.

    Inventor： Min Chang KIM ,  Woo Yeol SHIN ,  Noh Hyup KWAK

    IPC: G11C29/12 ,  G11C7/22

    CPC classification number: G11C29/1201 ,  G11C7/222 ,  G11C29/12015

    Abstract: A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device. The second semiconductor device may include a selective transfer unit configured to electrically couple the third pad group to the first pad group or to an interface unit electrically coupled to the first pad group, in response to a test mode enable signal.

    Abstract translation: 半导体系统可以包括包括第一焊盘组的第一半导体器件。 该半导体系统可以包括第二半导体器件，该第二半导体器件包括第二焊盘组，其被配置用于输入和输出来自第三半导体器件的信号。 第二半导体器件可以包括选择性传输单元，其被配置为响应于测试模式使能信号将第三焊盘组电耦合到第一焊盘组或电耦合到第一焊盘组的接口单元。

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