公开(公告)号：US20200293199A1

公开(公告)日：2020-09-17

申请号：US16889249

申请日：2020-06-01

申请人： SK hynix Inc.

发明人： Won Ha CHOI ,  Oung Sic CHO ,  Jong Hoon OH ,  Hyuk Choong KANG

IPC分类号： G06F3/06

摘要： A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

公开(公告)号：US20160118983A1

公开(公告)日：2016-04-28

申请号：US14661687

申请日：2015-03-18

申请人： SK hynix Inc.

发明人： Oung Sic CHO ,  Jong Hoon OH

IPC分类号： H03K19/00

CPC分类号： H03K19/0005

摘要： A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

摘要翻译： 共享用于阻抗匹配的电阻器的校准电路包括命令解码器，其被配置为接收命令信号并将命令信号解码为校准使能信号; 选择器，被配置为根据选择信号选择校准使能信号和起始信号之一，并提供驱动信号; 以及校准驱动器，被配置为响应于所述驱动信号执行阻抗匹配操作，并且当执行完成时产生完成信号，其中所述起始信号对应于从另一个校准电路提供的完成信号，该校准电路共享用于阻抗匹配的电阻器 。

公开(公告)号：US20150188566A1

公开(公告)日：2015-07-02

申请号：US14288232

申请日：2014-05-27

申请人： SK HYNIX INC.

发明人： Sang Eun LEE ,  Chang il KIM ,  Oung Sic CHO

IPC分类号： H03M7/30 ,  G06F13/42

CPC分类号： H03M7/6058 ,  H03M7/48

摘要： A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.

摘要翻译： 数据处理装置包括压缩电路和填充电路。 压缩电路被配置为比较由2n比特（其中n是自然数）组成的数据内的两个连续比特的对，并且基于比较的结果来压缩数据。 填充电路被配置为通过用虚拟焊盘填充压缩数据来生成2n位的发送数据。

公开(公告)号：US20200295757A1

公开(公告)日：2020-09-17

申请号：US16889253

申请日：2020-06-01

申请人： SK hynix Inc.

发明人： Won Ha CHOI ,  Oung Sic CHO ,  Jong Hoon OH

IPC分类号： H03K19/00

摘要： A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.

公开(公告)号：US20150155022A1

公开(公告)日：2015-06-04

申请号：US14252479

申请日：2014-04-14

申请人： SK HYNIX INC.

发明人： Sang Eun LEE ,  Oung Sic CHO

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： A data processing apparatus includes a controller configured to provide, using a unified connector, group data processing information for a processing operation of a data group processed based on the same data processing information. The data group comprises a plurality data transmitted or received through a plurality of connectors. An operation unit is configured to decode and/or encode the data group based on the group data processing information.

摘要翻译： 数据处理装置包括：控制器，被配置为使用统一的连接器提供用于基于相同数据处理信息处理的数据组的处理操作的组数据处理信息。 数据组包括通过多个连接器发送或接收的多个数据。 操作单元被配置为基于组数据处理信息对数据组进行解码和/或编码。

公开(公告)号：US20200059233A1

公开(公告)日：2020-02-20

申请号：US16661685

申请日：2019-10-23

申请人： SK hynix Inc.

发明人： Oung Sic CHO ,  Jong Hoon OH

IPC分类号： H03K19/00

摘要： A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

公开(公告)号：US20180351555A1

公开(公告)日：2018-12-06

申请号：US16101998

申请日：2018-08-13

申请人： SK hynix Inc.

发明人： Oung Sic CHO ,  Jong Hoon OH

IPC分类号： H03K19/00

CPC分类号： H03K19/0005

摘要： A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

公开(公告)号：US20170288669A1

公开(公告)日：2017-10-05

申请号：US15626648

申请日：2017-06-19

申请人： SK hynix Inc.

发明人： Oung Sic CHO ,  Jong Hoon OH

IPC分类号： H03K19/00

CPC分类号： H03K19/0005

摘要： A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

公开(公告)号：US20150280709A1

公开(公告)日：2015-10-01

申请号：US14307617

申请日：2014-06-18

申请人： SK Hynix Inc.

发明人： Oung Sic CHO ,  Sang Eun LEE

IPC分类号： H03K19/00 ,  G05F1/652 ,  H03K3/012

CPC分类号： H03K19/0005 ,  G05F1/652 ,  H03K3/012 ,  H03K19/00369

摘要： The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.

摘要翻译： 半导体器件包括：第一管芯，被配置为包括第一输入焊盘和第一输出焊盘; 以及第二管芯，被配置为包括第二输入焊盘和第二输出焊盘。 第二模具响应于从第一输出焊盘施加到第二输入焊盘的反馈参考电压校正输出电压的电平。

公开(公告)号：US20150186309A1

公开(公告)日：2015-07-02

申请号：US14286911

申请日：2014-05-23

申请人： SK hynix Inc.

发明人： Sang Eun LEE ,  Chang il KIM ,  Oung Sic CHO

IPC分类号： G06F13/28 ,  G06F13/16

CPC分类号： G06F13/1678 ,  G06F11/27 ,  G06F13/385 ,  G06F17/30424

摘要： A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

摘要翻译： 数据处理装置包括控制器。 控制器包括：压缩电路，被配置为比较多个数据组，每个数据组具有第一突发长度，并以预定模式以输入/输出宽度为单位发送，并且基于数据组基于 比较的结果。 控制器还包括压缩数据重构电路，该压缩数据重构电路经配置以通过重构压缩数据组以产生第二突发长度来生成传输数据组。