公开(公告)号：US20170373010A1

公开(公告)日：2017-12-28

申请号：US15699741

申请日：2017-09-08

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Seung Taek YANG

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2224/05599 ,  H01L2224/13099

Abstract: A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. The semiconductor device may include a top package stacked over the middle package, and embedded with at least two third semiconductor chips.

公开(公告)号：US20140124921A1

公开(公告)日：2014-05-08

申请号：US13799362

申请日：2013-03-13

Applicant: SK HYNIX INC.

Inventor： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

IPC: H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/16 ,  H01L23/3128 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15311

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract translation: 半导体封装包括基板; 驱动芯片，其在第一表面上具有第一凸块，并且在第二表面上具有凸起焊盘，所述第二表面背离所述第一表面，并且通过所述第一凸块的介质安装到所述基板; 相对于所述驱动芯片基本上水平地布置在所述基板上的支撑构件; 以及基本上水平地设置在驱动芯片和支撑构件上的多个存储器芯片，使得存储芯片的一个角部位于驱动芯片上，同时围绕驱动芯片居中，其中各个存储器芯片具有第二凸块， 在与驱动芯片相对的存储芯片的一个角部的一个表面上与驱动芯片的各个凸块焊盘电连接。

公开(公告)号：US20150155022A1

公开(公告)日：2015-06-04

申请号：US14252479

申请日：2014-04-14

Applicant: SK HYNIX INC.

Inventor： Sang Eun LEE ,  Oung Sic CHO

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A data processing apparatus includes a controller configured to provide, using a unified connector, group data processing information for a processing operation of a data group processed based on the same data processing information. The data group comprises a plurality data transmitted or received through a plurality of connectors. An operation unit is configured to decode and/or encode the data group based on the group data processing information.

Abstract translation: 数据处理装置包括：控制器，被配置为使用统一的连接器提供用于基于相同数据处理信息处理的数据组的处理操作的组数据处理信息。 数据组包括通过多个连接器发送或接收的多个数据。 操作单元被配置为基于组数据处理信息对数据组进行解码和/或编码。

公开(公告)号：US20140284795A1

公开(公告)日：2014-09-25

申请号：US14011930

申请日：2013-08-28

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Chang Il KIM

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L23/13 ,  H01L23/49883 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/06155 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/24997 ,  H01L2224/25175 ,  H01L2224/2612 ,  H01L2224/27436 ,  H01L2224/27442 ,  H01L2224/29015 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8201 ,  H01L2224/82097 ,  H01L2224/82105 ,  H01L2224/82138 ,  H01L2224/82143 ,  H01L2224/82385 ,  H01L2224/82815 ,  H01L2224/8291 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected.

Abstract translation: 各种实施例涉及半导体封装及其制造方法。 半导体封装包括以下：具有多个连接焊盘的衬底; 半导体芯片，其在其第一表面上设置有多个接合焊盘，并以面朝下的位置附接到所述基板上，使得所述接合焊盘位于相应的连接焊盘的正上方; 以及引入在基板和半导体芯片之间的热塑性导电构件，使得焊盘和相应的连接焊盘可以电连接。

公开(公告)号：US20160329298A1

公开(公告)日：2016-11-10

申请号：US14809710

申请日：2015-07-27

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Seung Taek YANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L27/108 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2224/05599 ,  H01L2224/13099

Abstract: A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over the bottom package, and embedded with at least two second semiconductor chips in a fan-out structure. The semiconductor device may include a top package stacked over the middle package, and embedded with at least two third semiconductor chips.

Abstract translation: 半导体器件可以包括嵌入有第一半导体芯片的底部封装。 半导体器件可以包括堆叠在底部封装上的中间封装，并且以扇出结构嵌入至少两个第二半导体芯片。 半导体器件可以包括堆叠在中间封装上的顶部封装，并且嵌入至少两个第三半导体芯片。

公开(公告)号：US20150280709A1

公开(公告)日：2015-10-01

申请号：US14307617

申请日：2014-06-18

Applicant: SK Hynix Inc.

Inventor： Oung Sic CHO ,  Sang Eun LEE

IPC: H03K19/00 ,  G05F1/652 ,  H03K3/012

CPC classification number: H03K19/0005 ,  G05F1/652 ,  H03K3/012 ,  H03K19/00369

Abstract: The semiconductor device includes: a first die configured to include a first input pad and a first output pad; and a second die configured to include a second input pad and a second output pad. The second die corrects a level of an output voltage in response to a feedback reference voltage applied from the first output pad to the second input pad.

Abstract translation: 半导体器件包括：第一管芯，被配置为包括第一输入焊盘和第一输出焊盘; 以及第二管芯，被配置为包括第二输入焊盘和第二输出焊盘。 第二模具响应于从第一输出焊盘施加到第二输入焊盘的反馈参考电压校正输出电压的电平。

公开(公告)号：US20150186309A1

公开(公告)日：2015-07-02

申请号：US14286911

申请日：2014-05-23

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Chang il KIM ,  Oung Sic CHO

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/1678 ,  G06F11/27 ,  G06F13/385 ,  G06F17/30424

Abstract: A data processing device includes a controller. The controller includes a compression circuit configured to compare a plurality of data groups, each of which has a first burst length and is transmitted in units of an input/output width, with a predetermined pattern, and perform data compression on the data groups based on a result of comparison. The controller further includes a compression data restructuring circuit configured to generate a transmission data group by restructuring the compressed data group to have a second burst length.

Abstract translation: 数据处理装置包括控制器。 控制器包括：压缩电路，被配置为比较多个数据组，每个数据组具有第一突发长度，并以预定模式以输入/输出宽度为单位发送，并且基于数据组基于 比较的结果。 控制器还包括压缩数据重构电路，该压缩数据重构电路经配置以通过重构压缩数据组以产生第二突发长度来生成传输数据组。

公开(公告)号：US20140117430A1

公开(公告)日：2014-05-01

申请号：US13798800

申请日：2013-03-13

Applicant: SK HYNIX INC.

Inventor： Sang Eun LEE ,  Sung Soo RYU ,  Chang Il KIM ,  Seon Kwang JEON

IPC: H01L25/18

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.

Abstract translation: 半导体封装包括第一衬底，水平地设置在第一衬底上的多个存储器芯片，并且具有面对第一衬底的一个表面，远离一个表面的其他表面以及形成在其它表面上的第一凸块， 第二基板，设置在所述多个存储器芯片上并电连接;副基板，与所述多个存储器芯片一起水平地设置在所述第一基板上，并且电连接所述第一基板和所述第二基板;以及驱动芯片， 并且安装到第二基板，使得第二凸块与第二基板电连接。

公开(公告)号：US20170317056A1

公开(公告)日：2017-11-02

申请号：US15221920

申请日：2016-07-28

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/49827 ,  H01L23/525 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/1436 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/1703

Abstract: The present disclosure provides a semiconductor chip including a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip includes a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip includes a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.

公开(公告)号：US20170084575A1

公开(公告)日：2017-03-23

申请号：US14969241

申请日：2015-12-15

Applicant: SK hynix Inc.

Inventor： Sang Eun LEE ,  Eun KO ,  Yong Jae PARK

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor package may be provided. The semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip flip-chip bonded to a first surface of the substrate. The semiconductor package may include second semiconductor chips respectively flip-chip bonded to portions of the first surface of the substrate adjacent to both ends of the first semiconductor chip. The semiconductor package may include a third semiconductor chip solder-jointed to the first surface of the substrate covering the first semiconductor chip and portions of the second semiconductor chips.