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公开(公告)号:US20190115052A1
公开(公告)日:2019-04-18
申请号:US15984803
申请日:2018-05-21
Applicant: SK hynix Inc.
Inventor: Jin Yong SEONG , Ho Jun KANG , Sang Bin PARK
Abstract: Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.
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公开(公告)号:US20160124640A1
公开(公告)日:2016-05-05
申请号:US14657765
申请日:2015-03-13
Applicant: SK hynix Inc.
Inventor: Sang Bin PARK
CPC classification number: G06F3/061 , G06F3/0655 , G06F3/0685 , G06F3/0688 , G06F12/0246 , G06F12/0802 , G06F2212/1016 , G06F2212/2022 , G06F2212/221 , G06F2212/7201
Abstract: A memory system includes a first control circuit part configured to communicate with a host through a first host channel, a second control circuit part configured to communicate with the host through a second host channel, a first chip group configured to communicate with the first control circuit part through a first internal channel, and a second chip group configured to communicate with the second control circuit part through a second internal channel, wherein the first control circuit part and the second control circuit part alternately receive a plurality of data inputted through one of the first and second host channels, which is selected during a single channel operation, and transmit the data to the first chip group and the second chip group.
Abstract translation: 存储器系统包括被配置为通过第一主机通道与主机进行通信的第一控制电路部分,被配置为通过第二主机通道与主机通信的第二控制电路部分,被配置为与第一控制电路通信的第一芯片组 以及第二芯片组,被配置为通过第二内部通道与第二控制电路部分通信,其中第一控制电路部分和第二控制电路部分交替地接收通过第一内部通道之一输入的多个数据 在单个信道操作期间选择的第一和第二主机信道,并将数据发送到第一芯片组和第二芯片组。
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