-
公开(公告)号：US10943629B2
公开(公告)日：2021-03-09
申请号：US16730206
申请日：2019-12-30
申请人： SK hynix Inc.
发明人： Seung Hun Lee , Hyeong Soo Jeong
摘要： A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates a plurality of operation codes and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on at least a part of an operation code, among the plurality of operation codes, and the strobe pulse, and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys, after the seed signal is generated, based on the plurality of operation codes and the strobe pulse, and prevents the generation of the enable signal when any one of the plurality of guard keys is disabled.
-
公开(公告)号：US10725495B2
公开(公告)日：2020-07-28
申请号：US16507516
申请日：2019-07-10
申请人： Sk hynix Inc.
发明人： Woongrae Kim , Seung Hun Lee
IPC分类号： G06F1/04 , G06F1/3203 , G11C5/14 , H03K3/012
摘要： A power gating system includes a logic circuit region including at least one logic gate configured to receive a first gating clock signal. The power gating system also includes a power gating control circuit configured to generate the first gating clock signal which is controlled to start transition after stabilization of an internal power voltage according to a chip select signal, a command/address signal, and an external clock signal.
-
公开(公告)号：US10133284B2
公开(公告)日：2018-11-20
申请号：US15694336
申请日：2017-09-01
申请人： SK hynix Inc.
发明人： Seung Hun Lee , Won Kyung Chung
摘要： A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
-
公开(公告)号：US10734042B2
公开(公告)日：2020-08-04
申请号：US16506648
申请日：2019-07-09
申请人： SK hynix Inc.
发明人： Woongrae Kim , Myung Kyun Kwak , Seung Hun Lee
摘要： A semiconductor device includes an input/output (I/O) control signal generation circuit, a pipe circuit and an auto-pre-charge signal generation circuit. The I/O control signal generation circuit generates an input control signal, an output control signal and an internal output control signal. The pipe circuit latches an internal command/address signal based on the input control signal and outputs the latched internal command/address signal as a latch signal. The auto-pre-charge signal generation circuit generates an auto-pre-charge signal from the latch signal and the internal latch signal.
-
公开(公告)号：US09785158B2
公开(公告)日：2017-10-10
申请号：US15041258
申请日：2016-02-11
申请人： SK hynix Inc.
发明人： Seung Hun Lee , Won Kyung Chung
摘要： A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
-
公开(公告)号：US11495276B2
公开(公告)日：2022-11-08
申请号：US17354815
申请日：2021-06-22
申请人： SK hynix Inc.
发明人： Woongrae Kim , Kyung Mook Kim , Seung Hun Lee , Da In Im
摘要： An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.
-
公开(公告)号：US10762935B2
公开(公告)日：2020-09-01
申请号：US16400680
申请日：2019-05-01
申请人： SK hynix Inc.
发明人： Myung Kyun Kwak , Woongrae Kim , Seung Hun Lee
摘要： A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.
-
公开(公告)号：US10523215B2
公开(公告)日：2019-12-31
申请号：US16012453
申请日：2018-06-19
申请人： SK hynix Inc.
发明人： Seung Hun Lee , Sang Sic Yoon
摘要： A semiconductor apparatus may include a synchronization circuit, and a phase detection circuit. The synchronization circuit may be configured to, based on an operation mode of the semiconductor apparatus, divide a first clock signal to generate first and second divided clock signals or divide a phase-locked clock signal to generate first and second divided clock signals. The phase detection circuit may be configured to use, based on the operation mode of the semiconductor apparatus, either the first and second clock signals created from dividing the first clock signal or the first and second clock signals created from dividing the phase-locked clock signal, to compare either the first divided clock signal or the second divided clock signal with a second clock signal to generate a phase detection signal.
-
9.发明授权公开(公告)号：US11483505B2
公开(公告)日：2022-10-25
申请号：US16769830
申请日：2018-06-14
申请人： SK hynix Inc.
发明人： Chang Hyun Kim , Wan Jun Roh , Doo Bock Lee , Seung Hun Lee , Jae Jin Lee , Chun Seok Jeong
摘要： In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.
-
公开(公告)号：US11315621B2
公开(公告)日：2022-04-26
申请号：US17009329
申请日：2020-09-01
申请人： SK hynix Inc.
发明人： Kyung Mook Kim , Woongrae Kim , Sang Il Park , Seung Hun Lee
IPC分类号： G11C11/406 , G11C11/408 , G11C11/4074
摘要： A device includes an operation control circuit and a drive control signal generation circuit. The operation control circuit generates an internal refresh signal that is activated to perform an active operation for a cell array, the cell array being coupled to a word line that is selected by a row address based on a refresh signal that is activated to perform a refresh operation. In addition, the operation control circuit generates a pre-refresh pulse based on the refresh signal and generates a refresh end pulse based on the internal refresh signal. The drive control signal generation circuit generates a drive control signal to control a drive of an active voltage that is supplied to the word line that is selected by the row address based on the internal refresh signal, the pre-refresh pulse, and the refresh end pulse.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.013 秒)
