公开(公告)号：US20200258592A1

公开(公告)日：2020-08-13

申请号：US16860566

申请日：2020-04-28

Applicant: SK hynix Inc.

Inventor： Sang-Hyun BAN ,  Tae-Hoon KIM ,  Woo-Tae LEE ,  Hye-Jung CHOI

IPC: G11C29/50 ,  G11C29/12 ,  G11C29/00 ,  G11C29/46 ,  G06F1/24

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

公开(公告)号：US20200058870A1

公开(公告)日：2020-02-20

申请号：US16412273

申请日：2019-05-14

Applicant: SK hynix Inc.

Inventor： Woo-Tae LEE ,  Gwang-Sun JUNG ,  Tae-Hoon KIM ,  Sang-Hyun BAN ,  Beom-Seok LEE ,  Uk HWANG

IPC: H01L45/00 ,  C01G28/00

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic and 40-50 at % of selenium. The electronic device may include a semiconductor memory device, the semiconductor memory device including a first memory cell that includes a first switching element. The first switching element may include a chalcogenide material including 0.1-5 atomic percent (at %) of silicon, 15-22 at % of germanium, 30-35 at % of arsenic, and 40-50 at % of selenium.

公开(公告)号：US20180182468A1

公开(公告)日：2018-06-28

申请号：US15854587

申请日：2017-12-26

Applicant: SK hynix Inc.

Inventor： Sang-Hyun BAN ,  Tae-Hoon KIM ,  Woo-Tae LEE ,  Hye-Jung CHOI

IPC: G11C29/50 ,  G06F1/24

CPC classification number: G11C29/50004 ,  G06F1/24 ,  G11C29/12005 ,  G11C29/46 ,  G11C29/50008 ,  G11C29/883 ,  G11C2029/5004

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.

公开(公告)号：US20200381073A1

公开(公告)日：2020-12-03

申请号：US16997652

申请日：2020-08-19

Applicant: SK hynix Inc.

Inventor： Sang-Hyun BAN ,  Tae-Hoon KIM ,  Woo-Tae LEE ,  Hye-Jung CHOI

IPC: G11C29/50 ,  H01L45/00 ,  H01L27/24 ,  G11C11/16 ,  H01L43/08 ,  G11C13/00 ,  G06F12/0802 ,  H01L27/22 ,  H01L23/528

Abstract: A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state.

公开(公告)号：US20200058871A1

公开(公告)日：2020-02-20

申请号：US16412287

申请日：2019-05-14

Applicant: SK hynix Inc.

Inventor： Woo-Tae LEE

IPC: H01L45/00 ,  C01G28/00

Abstract: A chalcogenide material and an electronic device are provided. The chalcogenide material may include 1-10 atomic percent (at %) of silicon, 10-20 at % of germanium, 25-35 at % of arsenic, 40-50 at % of selenium, and 1-10 at % of tellurium. The electronic device may include a switching element including a chalcogenide material, the chalcogenide material including 1-10 atomic percent (at %) of silicon, 10-20 at % of germanium, 25-35 at % of arsenic, 40-50 at % of selenium, and 1-10 at % of tellurium. The electronic device may further include a first electrode electrically coupled to the switching element and a second electrode electrically coupled to the switching element.

公开(公告)号：US20160284992A1

公开(公告)日：2016-09-29

申请号：US14856488

申请日：2015-09-16

Applicant: SK hynix Inc.

Inventor： Woo-Tae LEE

IPC: H01L45/00 ,  G06F12/08 ,  G06F13/16 ,  H01L27/24

CPC classification number: H01L45/08 ,  G06F12/0868 ,  G06F12/0875 ,  G06F13/1673 ,  G06F2212/451 ,  G06F2212/452 ,  H01L27/2427 ,  H01L27/249 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1633

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a vertical electrode layer formed over a substrate and extending in a vertical direction substantially perpendicular to a surface of the substrate; an interlayer dielectric layer and a structure formed over the substrate and alternately stacked along the vertical electrode layer, wherein the structure includes a horizontal electrode layer and a base layer which is conductive and located over or under the horizontal electrode layer; a variable resistance layer interposed between the vertical electrode layer and the base layer, and including a common element with the base layer; and a groove interposed between the vertical electrode layer and the horizontal electrode layer and insulating the vertical electrode layer and the horizontal electrode layer from each other.

Abstract translation: 电子设备包括半导体存储器。 半导体存储器包括垂直电极层，该垂直电极层形成在衬底上并且在基本上垂直于衬底的表面的垂直方向上延伸; 层叠介电层和形成在所述基板上并且沿着所述垂直电极层交替堆叠的结构，其中所述结构包括导电并位于所述水平电极层之上或之下的水平电极层和基极层; 插入在所述垂直电极层和所述基底层之间的可变电阻层，并且包括与所述基底层的共同元件; 以及插入在所述垂直电极层和所述水平电极层之间并且将所述垂直电极层和所述水平电极层彼此绝缘的沟槽。