公开(公告)号：US09311985B2

公开(公告)日：2016-04-12

申请号：US14298581

申请日：2014-06-06

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Choung Ki Song

IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C7/02 ,  G11C11/408

CPC分类号： G11C11/40615 ,  G11C7/02 ,  G11C11/406 ,  G11C11/4087

摘要： A memory includes a plurality of word lines, a target address generation unit generating one or more target addresses by using a stored address, a refresh control section activating a refresh signal in response to a refresh command that is periodically inputted and periodically activating the refresh signal in a self-refresh mode, a target refresh control section activating a target refresh signal when the refresh signal is activated M times, wherein the M is a natural number, and deactivating the target refresh signal in the self-refresh mode, and a row control section sequentially refresh a plurality of first word lines in response to the refresh signal and refreshing a second word line corresponding to the target address in response to the refresh signal when the target refresh signal is activated.

摘要翻译： 存储器包括多个字线，通过使用存储的地址生成一个或多个目标地址的目标地址生成单元，响应于周期性地输入的刷新命令来激活刷新信号的刷新控制部分，并周期地激活刷新信号 在自刷新模式中，当刷新信号被激活M次时激活目标刷新信号的目标刷新控制部分，其中M是自然数，并且在自刷新模式中去激活目标刷新信号，并且行 控制部分响应于刷新信号顺序刷新多个第一字线，并且当目标刷新信号被激活时响应于刷新信号刷新对应于目标地址的第二字线。

公开(公告)号：US09123406B2

公开(公告)日：2015-09-01

申请号：US14293649

申请日：2014-06-02

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Chang-Hyun Kim ,  Choung-Ki Song

IPC分类号： G11C8/18 ,  G11C8/08 ,  G11C8/06 ,  G11C8/10

CPC分类号： G11C8/18

摘要： A semiconductor memory device includes a clock signal generation unit suitable for dividing an external clock signal to generate a first internal clock signal corresponding to odd number periods of the external clock signal and a second internal clock corresponding to even number periods, a first input unit suitable for receiving an external command signal and an external address signal in response to the first internal clock signal, a second input unit suitable for receiving the external command signal and the external address signal in response to the second internal clock signal, and an operation control unit suitable for enabling one of the first input unit and the second input unit and disabling the other of the first input unit and the second input unit, during a gear-down mode.

摘要翻译： 半导体存储器件包括：时钟信号生成单元，适于分割外部时钟信号以产生对应于外部时钟信号的奇数周期的第一内部时钟信号和对应于偶数周期的第二内部时钟;第一输入单元， 用于响应于第一内部时钟信号接收外部命令信号和外部地址信号，第二输入单元适于响应于第二内部时钟信号接收外部命令信号和外部地址信号;以及操作控制单元 适于在减速模式期间启用第一输入单元和第二输入单元中的一个并禁用第一输入单元和第二输入单元中的另一个。

公开(公告)号：US11139041B2

公开(公告)日：2021-10-05

申请号：US16668129

申请日：2019-10-30

申请人： SK hynix Inc.

发明人： Yo-Sep Lee

IPC分类号： G11C29/14 ,  H01L25/065 ,  H03K21/38 ,  G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/36 ,  G11C29/18 ,  G11C8/06

摘要： A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.

公开(公告)号：US08873326B2

公开(公告)日：2014-10-28

申请号：US13717944

申请日：2012-12-18

申请人： SK Hynix Inc.

发明人： Yo-Sep Lee

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/40611 ,  G11C11/40618

摘要： A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

摘要翻译： 存储器件包括多个存储器块，其被配置为响应于相应的刷新信号刷新; 命令解码器，被配置为解码外部输入命令以产生内部刷新命令; 刷新控制单元，被配置为当所述内部刷新命令被激活并且设置了第一模式时激活对应于所述第一数量的存储器块的第一数量的刷新信号，并且激活与所述第二数量的对应的第二数量的刷新信号 当内部刷新命令被激活并且设置了第二模式时，存储器块，第二个数字小于第一个数字; 以及地址计数器，被配置为当预定的刷新信号被激活时，改变传送到存储器块的行地址。

公开(公告)号：US11289174B2

公开(公告)日：2022-03-29

申请号：US16849512

申请日：2020-04-15

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Dong-Ha Lee ,  Seon-Woo Hwang

IPC分类号： G11C29/56 ,  G11C29/18 ,  G11C29/12 ,  H01L25/18 ,  H01L23/48

摘要： A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.

公开(公告)号：US09484079B2

公开(公告)日：2016-11-01

申请号：US14732354

申请日：2015-06-05

申请人： SK hynix Inc.

发明人： Yo-Sep Lee

IPC分类号： G11C11/406

CPC分类号： G11C11/40626

摘要： A memory device may include a temperature sensor suitable for generating temperature information and a smart refresh circuit suitable for activating a smart refresh signal when an internal refresh signal is activated a set number of times, and controlling the set number based on the temperature information.

摘要翻译： 存储装置可以包括适于产生温度信息的温度传感器和适于在内部刷新信号被激活一定次数时激活智能刷新信号的智能刷新电路，以及基于温度信息来控制设定数量。

公开(公告)号：US09484902B2

公开(公告)日：2016-11-01

申请号：US14796933

申请日：2015-07-10

申请人： SK hynix Inc.

发明人： Yo-Sep Lee

IPC分类号： H03K5/135 ,  H03K23/66 ,  H03K5/00

CPC分类号： H03K5/135 ,  H03K23/66 ,  H03K2005/00241 ,  H03K2005/00293

摘要： A delay circuit may include a fine timing measurement unit suitable for measuring fine timing information on whether an input signal corresponds to the timing of any one of an even cycle or an odd cycle based on a clock, a coarse delay unit suitable for delaying the input signal whose fine timing has been measured by the fine timing measurement unit in synchronization with a frequency divided clock and outputting a delayed signal, and a fine timing application unit suitable for applying the fine timing information to the delayed signal of the coarse delay unit.

摘要翻译： 延迟电路可以包括适合于测量关于输入信号是否对应于基于时钟的偶数周期或奇数周期中的任一个的定时的精细定时信息的精细定时测量单元，适于延迟输入的粗延迟单元 信号，其精细定时由精细定时测量单元与分频时钟同步并输出延迟信号，精度定时应用单元适用于将精细定时信息应用于粗延迟单元的延迟信号。

公开(公告)号：US09202549B2

公开(公告)日：2015-12-01

申请号：US14098032

申请日：2013-12-05

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Jung-Hyun Kim

IPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4087

摘要： A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (N) number of adjacent word lines during a target activation mode, and a mode exit control unit suitable for counting the number of activation operations by the row control unit during the target activation mode to determine whether or not to exit from the target activation mode.

摘要翻译： 半导体存储器件包括多个字线，每个字线连接到多个存储器单元，行控制单元适于顺序地激活和预充电对应于目标地址的字线和预定（N）个相邻字 在目标激活模式期间的线路以及模式退出控制单元，其适于在目标激活模式期间对行控制单元的激活操作次数进行计数，以确定是否退出目标激活模式。

公开(公告)号：US09123447B2

公开(公告)日：2015-09-01

申请号：US14109582

申请日：2013-12-17

申请人： SK hynix Inc.

发明人： Yo-Sep Lee ,  Choung-Ki Song

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C29/02 ,  G11C29/08 ,  G11C29/12

CPC分类号： G11C29/50012 ,  G11C29/025 ,  G11C29/08 ,  G11C2029/1202 ,  G11C2029/5002

摘要： A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.

摘要翻译： 存储器可以包括连接一个或多个存储器单元的多个字线，以及适于在目标刷新期间基于高激活字线的地址来选择的第一字线的激活和预充电的控制单元 在刷新操作中顺序地激活和预充电多个字线的操作，其中所述控制单元适合于在测试模式期间的目标刷新操作期间将测试数据写入连接到第一字线的一个或多个第一存储器单元， 其中所述高激活字线是在所述多个字线中的参考数字或参考频率上激活的字线。

公开(公告)号：US09030904B2

公开(公告)日：2015-05-12

申请号：US13714331

申请日：2012-12-13

申请人： SK Hynix Inc.

发明人： Yo-Sep Lee

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C29/02 ,  G11C29/50 ,  G06F1/32

CPC分类号： G11C7/00 ,  G06F1/3203 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016

摘要： A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

摘要翻译： 存储装置包括多个存储块，设置电路被配置为设置其中一次刷新第一数量的存储块的第一模式和第二模式，其中第二数量的存储块被刷新在 在存储器控制器的控制下，第二数量小于第一数量的时间，被配置为存储附加刷新信息的存储电路，以及刷新控制单元，被配置为控制一次刷新的第二数量的存储器块 每当在附加刷新信息被去激活时应用刷新命令，并且当在第二模式的情况下激活附加刷新信息时，每当施加刷新命令时，一次控制要刷新的第一数量的存储器块 由设定电路设定。