公开(公告)号：US20200076442A1

公开(公告)日：2020-03-05

申请号：US16410793

申请日：2019-05-13

Applicant: SOCIONEXT INC.

Inventor： Hassan SHAFEEU ,  Vlad CRETU ,  Nicolas RIVAT

IPC: H03M1/10 ,  G05F3/26 ,  H03K5/24 ,  H03M1/68

Abstract: Current-generation circuitry, comprising: a plurality of candidate current sources operable to generate respective candidate currents; an output current source operable to generate an output current; comparator circuitry; and control circuitry operable to control the current sources and the comparator circuitry to: in an adjustment step, generate an adjustment current by selecting one of the candidate currents or by summing together a plurality of the candidate currents, and calibrate at least a plurality of the candidate current sources; and in a calibration step, following the adjustment step, generate a reference current by selecting one of the candidate currents generated by the candidate current sources calibrated in the adjustment step or by summing together a plurality of the candidate currents generated by those candidate current sources, and calibrate the output current source by comparing its output current to that reference current and adjusting a control signal applied to that output current source.

公开(公告)号：US20220407513A1

公开(公告)日：2022-12-22

申请号：US17834653

申请日：2022-06-07

Applicant: SOCIONEXT INC

Inventor： Vlad CRETU ,  Masahiro KUDO

IPC: H03K17/687

Abstract: A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.

公开(公告)号：US20220407535A1

公开(公告)日：2022-12-22

申请号：US17837615

申请日：2022-06-10

Applicant: Socionext Inc.

Inventor： Vlad CRETU ,  Armin JALILI SEBARDAN

IPC: H03M1/12 ,  H03K17/54

Abstract: A sampling switch circuit, comprising an input node, connected to receive an input voltage signal, a sampling transistor comprising a gate terminal, a source terminal and a drain terminal, the source terminal connected to the input node, a hold-control node connected to receive a hold-control voltage signal, an output node connected to the drain terminal of the sampling transistor, a buffer circuit having a buffer input connected to the input node and a buffer output connected to a track-control node, the buffer circuit configured to provide a track-control voltage signal at the track-control node dependent on the input voltage signal and switching circuitry configured to connect the gate terminal of the sampling transistor to the track-control node or to the hold-control node in dependence upon a clock signal.

公开(公告)号：US20220407502A1

公开(公告)日：2022-12-22

申请号：US17837562

申请日：2022-06-10

Applicant: Socionext Inc.

Inventor： Vlad CRETU

IPC: H03H11/24

Abstract: Differential attenuation circuitry, including: first and second input nodes; first and second output nodes; and an impedance network connected between the first and second input nodes and the first and second output nodes to provide a differential output voltage signal between the first and second output nodes which is attenuated compared to a differential input voltage signal applied between the first and second input nodes, wherein the impedance network includes: a common-mode node; a first impedance network connected between the first input node, the common-mode node and the first output node; and a second impedance network connected between the second input node, the common-mode node and the second output node, and wherein the differential attenuation circuitry further includes: an input-to-input path comprising one or more impedances and one or more switches connected between the first and second input nodes to provide a current path independent of the common-mode node.

公开(公告)号：US20240079071A1

公开(公告)日：2024-03-07

申请号：US18454125

申请日：2023-08-23

Applicant: Socionext Inc.

Inventor： Sandeep SANTHOSH KUMAR ,  Vlad CRETU ,  Masahiro KUDO

IPC: G11C27/02 ,  H03K19/0185 ,  H03M1/12

CPC classification number: G11C27/02 ,  H03K19/018507 ,  H03M1/1245

Abstract: A sample and hold circuit includes: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.