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公开(公告)号：US20240079071A1
公开(公告)日：2024-03-07
申请号：US18454125
申请日：2023-08-23
Applicant: Socionext Inc.
Inventor： Sandeep SANTHOSH KUMAR , Vlad CRETU , Masahiro KUDO
IPC: G11C27/02 , H03K19/0185 , H03M1/12
CPC classification number: G11C27/02 , H03K19/018507 , H03M1/1245
Abstract: A sample and hold circuit includes: an input node to which an input voltage signal is configured to be supplied; a first reference voltage node to which a first reference voltage potential is configured to be supplied; a sampling capacitor circuit; a sampling switch transistor circuit connected between the input node and the sampling capacitor circuit; a first common mode switch transistor circuit connected between the sampling capacitor circuit and the first reference voltage node; a signal bootstrap circuit configured to generate a first control voltage based on a clock signal, the first control voltage varying according to a level of the input voltage signal, and configured to control the sampling switch transistor circuit based on the first control voltage; and a static bootstrap circuit configured to generate a second control voltage based on the clock signal, the second control voltage being programmable, and configured to control the first common mode switch transistor circuit based on the second control voltage.
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公开(公告)号：US20190109738A1
公开(公告)日：2019-04-11
申请号：US16209616
申请日：2018-12-04
Applicant: Socionext Inc.
Inventor： Masahiro KUDO , Daisuke Suzuki
Abstract: An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.
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公开(公告)号：US20180367103A1
公开(公告)日：2018-12-20
申请号：US16110801
申请日：2018-08-23
Applicant: Socionext Inc.
Inventor： Masahiro KUDO
CPC classification number: H03F1/30 , H03F3/45183 , H03F3/45766 , H03F3/45771 , H03F2200/447 , H03F2200/453 , H03F2203/45208 , H03F2203/45624 , H03F2203/45726 , H03G1/0029 , H03G1/0088 , H03G3/001 , H03G3/30 , H03K5/24
Abstract: An amplifier circuit includes: an input circuit configured to receive an input signal; a load circuit provided in series with the input circuit and including a first variable resistance unit and a second variable resistance unit, a resistance value of the first variable resistance unit being controlled by, a digital code, a resistance value of the second variable resistance unit being controlled by an analog control voltage; and a correction circuit including a third variable resistance unit having a circuit configuration corresponding to the first variable resistance unit and a fourth variable resistance unit having a circuit configuration corresponding to the second resistance unit, a resistance value of the third variable resistance unit being controlled by the digital code, a resistance value of the fourth variable resistance unit being controlled by the analog control voltage, the correction circuit being configured correct a resistance value of the load circuit.
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Patent Agency Ranking
公开(公告)号：US20180102897A1
公开(公告)日：2018-04-12
申请号：US15698044
申请日：2017-09-07
Applicant: Socionext Inc.
Inventor： Masahiro KUDO
CPC classification number: H04L7/0087 , H03L7/087 , H03L7/0891 , H04L7/0337 , H04L25/03019 , H04L25/4917
Abstract: A reception circuit includes a determination circuit including comparator circuits configured to determinate a level of a received signal and a logic circuit configured to generate a digital signal based on outputs of the comparator circuits. The determination circuit is configured to determinate by a first number of the comparator circuits when the received signal is a first signal which is a multi-valued signal and determinate by a second number of the comparator circuits, the second number being smaller than the first number, when the received signal is a second signal. The logic circuit is configured to operate as a decoder which decodes outputs of the comparator circuits and generates the digital signal when the received signal is the first signal, and operates as a selector which selects an output of the comparator circuit for generating the digital signal when the received signal is the second signal.
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公开(公告)号：US20230095506A1
公开(公告)日：2023-03-30
申请号：US18061757
申请日：2022-12-05
Applicant: Socionext Inc.
Inventor： Ryoichiro NAKAMURA , Masahiro KUDO
Abstract: An amplifier circuit according to an embodiment includes a first circuit, a second circuit, and a third circuit. The first circuit includes a first transistor connected between an input node through which an input current flows and a reference potential node. The first transistor has a gate electrode connected to the input node. The second circuit includes a low-pass filter circuit and a second transistor connected in parallel to the first transistor between the input node and the reference potential node. The second transistor has a gate electrode connected to the gate electrode of the first transistor via the low-pass filter circuit. The third circuit includes a third transistor connected between an output node through which an output current flows and the reference potential node, the third circuit having a gate electrode connected to the gate electrode of the first transistor.
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公开(公告)号：US20220407513A1
公开(公告)日：2022-12-22
申请号：US17834653
申请日：2022-06-07
Applicant: SOCIONEXT INC
Inventor： Vlad CRETU , Masahiro KUDO
IPC: H03K17/687
Abstract: A sampling switch circuit, including an input node, which receives an input voltage signal to be sampled, a sampling transistor having gate, source and drain terminals, the source terminal connected to the input node, a capacitor, a current source configured to cause a defined current to flow therethrough and switching circuitry configured to alternate between a precharge configuration and an output configuration depending upon a clock signal. In the precharge configuration, the switching circuitry connects the capacitor into a current path between said current source and a first voltage reference node to form a potential difference across the capacitor which is dependent on the defined current. In the output configuration, the switching circuitry connects the capacitor between a second voltage reference node and the gate terminal of the sampling transistor so that a voltage level applied at the gate terminal of the sampling transistor is dependent on the defined current.
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7.发明申请公开(公告)号：US20160344394A1
公开(公告)日：2016-11-24
申请号：US15090136
申请日：2016-04-04
Applicant: SOCIONEXT INC.
Inventor： Masahiro KUDO
CPC classification number: H04L7/0016 , H03K17/6257 , H03K17/693 , H03M9/00 , H04L25/03019
Abstract: A first P-channel transistor to a gate of which a first input signal is inputted and a second P-channel transistor to a gate of which a selection signal is inputted are provided in series between a power supply line and an output node. A first N-channel transistor to a gate of which a second input signal is inputted and a second N-channel transistor to a gate of which the selection signal is inputted are provided in series between a ground line and the output node. A third P-channel transistor to a gate of which the second input signal is inputted is provided between the gate of the second P-channel transistor and the output node, and a third N-channel transistor to a gate of which the first input signal is inputted is provided between the gate of the second N-channel transistor and the output node.
Abstract translation: 在电源线和输出节点之间串联地提供输入第一输入信号的栅极的第一P沟道晶体管和输入选择信号的栅极的第二P沟道晶体管。 将输入第二输入信号的栅极的第一N沟道晶体管和输入选择信号的栅极的第二N沟道晶体管串联提供在地线和输出节点之间。 输入第二输入信号的栅极的第三P沟道晶体管被提供在第二P沟道晶体管的栅极和输出节点之间，第三N沟道晶体管被提供到第一输入信号 被输入到第二N沟道晶体管的栅极和输出节点之间。
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公开(公告)号：US20160065189A1
公开(公告)日：2016-03-03
申请号：US14837870
申请日：2015-08-27
Applicant: Socionext Inc.
Inventor： Masahiro KUDO
CPC classification number: G06F13/38 , G06F13/4072 , G11C27/02 , H04L1/0045 , H04L7/0087 , H04L25/03
Abstract: A receiver circuit includes: a plurality of first holding circuits respectively latching a plurality of reception data pieces on the basis of a same clock signal; a comparison circuit respectively comparing first reception data pieces and second reception data pieces after a certain time elapses since the latch of the plurality of first holding circuits, the first reception date pieces being respectively latched by the plurality of first holding circuits, the second reception data pieces being respectively input to the plurality of first holding circuits; and a plurality of second holding circuits respectively latching the first reception data pieces when a first output signal of the comparison circuit indicates that the first reception data pieces and the second reception data pieces are identical.
Abstract translation: 接收机电路包括：多个第一保持电路，分别基于相同的时钟信号锁存多个接收数据; 比较电路，分别比较从多个第一保持电路的锁存开始经过一定时间之后的第一接收数据和第二接收数据片，第一接收日期片由多个第一保持电路分别锁存，第二接收数据 分别输入到多个第一保持电路; 以及多个第二保持电路，当比较电路的第一输出信号指示第一接收数据片段和第二接收数据片段相同时，分别锁存第一接收数据片段。
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