公开(公告)号：US20250081561A1

公开(公告)日：2025-03-06

申请号：US18952033

申请日：2024-11-19

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L27/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78

Abstract: A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

公开(公告)号：US20250015122A1

公开(公告)日：2025-01-09

申请号：US18888578

申请日：2024-09-18

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

Abstract: A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

公开(公告)号：US20240379410A1

公开(公告)日：2024-11-14

申请号：US18784161

申请日：2024-07-25

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12

Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US20240312831A1

公开(公告)日：2024-09-19

申请号：US18566474

申请日：2022-05-25

Applicant: SOITEC ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Alexis Drouin ,  Gweltaz Gaudin ,  Séverin Rouchier ,  Walter Schwarzenbach ,  Julie Widiez ,  Emmanuel Rolland

IPC: H01L21/762 ,  H01L21/04

CPC classification number: H01L21/76254 ,  H01L21/0445

Abstract: A method for producing a semiconductor structure comprises: a) provision of a monocrystalline silicon carbide donor substrate and a silicon carbide support substrate; b) production of a useful layer to be transferred, comprising—implanting light species in the donor substrate at a front face, so as to form a damage profile, the profile having a main peak of deep-level defects defining a buried brittle plane and a secondary peak of defects defining a damaged surface layer, and—removing the damaged surface layer by chemical etching and/or chemical mechanical polishing of the front face of the donor substrate, so as to form a new front surface of the donor substrate; c) assembly of donor substrate with the support substrate; and d) separation along the buried fragile plane, leading to the transfer of the useful layer onto the support substrate, so as to form the semiconductor structure.

公开(公告)号：US12074056B2

公开(公告)日：2024-08-27

申请号：US18047113

申请日：2022-10-17

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/84 ,  H01L27/1207 ,  H01L21/02532

Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

公开(公告)号：US20240145314A1

公开(公告)日：2024-05-02

申请号：US18402215

申请日：2024-01-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11552123B2

公开(公告)日：2023-01-10

申请号：US17133316

申请日：2020-12-23

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L27/146 ,  H01L21/762

Abstract: A front-side type image sensor may include a substrate successively including: a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.

公开(公告)号：US20210384223A1

公开(公告)日：2021-12-09

申请号：US17254808

申请日：2019-06-21

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Manuel Sellier ,  Ludovic Ecarnot

IPC: H01L27/12 ,  H01L27/146

Abstract: The invention relates to a front-side imager comprising in succession: —a semiconductor carrier substrate, a first electrically insulating separating layer, and a single-crystal semiconductor layer, called the active layer, comprising a matrix array of photodiodes, wherein the imager further comprises between the carrier substrate and the first electrically insulating layer: —a second electrically insulating separating layer, and —a second semiconductor or electrically conductive layer, called the intermediate layer, arranged between the second separating layer and the first separating layer, the second separating layer being thicker than the first separating layer.

公开(公告)号：US20200321243A1

公开(公告)日：2020-10-08

申请号：US16301276

申请日：2017-05-17

Applicant: SOITEC

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20190267425A1

公开(公告)日：2019-08-29

申请号：US16340879

申请日：2017-10-10

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L27/146 ,  H01L21/762

Abstract: A front-side type image sensor, includes a substrate successively comprising a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P− type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.