公开(公告)号：US20160351438A1

公开(公告)日：2016-12-01

申请号：US15159646

申请日：2016-05-19

Applicant: Soitec

Inventor： Ludovic Ecarnot ,  Nicolas Daval ,  Nadia Ben Mohamed ,  Francois Boedt ,  Carole David ,  Isabell Guerin

IPC: H01L21/762 ,  B28D5/00

CPC classification number: H01L21/76251 ,  B28D5/00 ,  H01L21/02002 ,  H01L21/76254

Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.

Abstract translation: 将被称为供体衬底的单晶衬底的层转移到接收器衬底上的方法包括：提供单晶施主衬底，具有沿晶体的第一方向取向的凹槽的衬底和包围晶体的弱区域 要转移的层，将单晶供体基板接合到接收器基板上，供体基板的与弱磁区相对的相对于待转移层的主表面在接合界面处，以及供体的分离 基底沿弱点区域。 在该方法中，施主衬底在与接收器衬底接合的主表面上具有基本上沿与第一方向不同的晶体的第二方向延伸的原子台阶阵列。

公开(公告)号：US20250015122A1

公开(公告)日：2025-01-09

申请号：US18888578

申请日：2024-09-18

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

Abstract: A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

公开(公告)号：US20240145314A1

公开(公告)日：2024-05-02

申请号：US18402215

申请日：2024-01-02

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US20200321243A1

公开(公告)日：2020-10-08

申请号：US16301276

申请日：2017-05-17

Applicant: SOITEC

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US10957577B2

公开(公告)日：2021-03-23

申请号：US16301276

申请日：2017-05-17

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US20190181035A1

公开(公告)日：2019-06-13

申请号：US16301260

申请日：2017-05-17

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76254 ,  H01L27/1203

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.

公开(公告)号：US12261079B2

公开(公告)日：2025-03-25

申请号：US18449298

申请日：2023-08-14

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.

公开(公告)号：US12100727B2

公开(公告)日：2024-09-24

申请号：US17418148

申请日：2019-12-23

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

CPC classification number: H01L27/14683 ,  H01L21/26506 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76254 ,  H01L27/1463 ,  H01L31/1892

Abstract: A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

公开(公告)号：US11876020B2

公开(公告)日：2024-01-16

申请号：US17250767

申请日：2019-09-03

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Nicolas Daval ,  Bich-Yen Nguyen ,  Guillaume Besnard

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/3247 ,  H01L21/7624

Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.

公开(公告)号：US11728207B2

公开(公告)日：2023-08-15

申请号：US17207202

申请日：2021-03-19

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Guillaume Chabanne ,  Nicolas Daval

IPC: H01L21/00 ,  H01L21/762

CPC classification number: H01L21/76275 ,  H01L21/76254

Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer. After transferring the monocrystalline semiconductor layer and before the cutting operation, a portion of the carrier substrate is selectively etched with respect to the intermediate layer, and the intermediate layer is selectively etched with respect to the monocrystalline semiconductor layer.