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    PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    3.
    发明申请
    PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
    用于磁阻随机存取存储器的基于柱状的互连

    公开(公告)号：US20110049655A1

    公开(公告)日：2011-03-03

    申请号：US12549799

    申请日：2009-08-28

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

    IPC分类号： H01L43/08 ,  H01L43/12

    CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L43/08

    摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

    摘要翻译： 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

    Method of forming vertical contacts in integrated circuits
    6.
    发明授权
    Method of forming vertical contacts in integrated circuits 有权
    在集成电路中形成垂直触点的方法

    公开(公告)号：US07803639B2

    公开(公告)日：2010-09-28

    申请号：US11619623

    申请日：2007-01-04

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    IPC分类号： H01L21/00 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L43/12 ,  H01L21/76807 ,  H01L21/76816

    摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

    摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

    Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit
    7.
    发明申请
    Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit 审中-公开
    利用侧壁间隔件在集成电路中形成磁隧道结

    公开(公告)号：US20080211055A1

    公开(公告)日：2008-09-04

    申请号：US12120915

    申请日：2008-05-15

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

    IPC分类号： H01L43/00 ,  H01L43/12

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

    摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
    8.
    发明授权
    Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
    利用侧壁间隔物特征在集成电路中形成磁隧道结

    公开(公告)号：US07531367B2

    公开(公告)日：2009-05-12

    申请号：US11333997

    申请日：2006-01-18

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  Sivananda Kanakasabapathy ,  John P. Hummel ,  David W. Abraham

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.

    摘要翻译： 描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。 根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。 有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。 此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

    Method of Forming Vertical Contacts in Integrated Circuits
    9.
    发明申请
    Method of Forming Vertical Contacts in Integrated Circuits 有权
    在集成电路中形成垂直触点的方法

    公开(公告)号：US20080164617A1

    公开(公告)日：2008-07-10

    申请号：US11619623

    申请日：2007-01-04

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L43/12 ,  H01L21/76807 ,  H01L21/76816

    摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

    摘要翻译： 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

    Method for fabricating synthetic antiferromagnetic (SAF) device
    10.
    发明授权
    Method for fabricating synthetic antiferromagnetic (SAF) device 有权
    制造合成反铁磁（SAF）装置的方法

    公开(公告)号：US09015927B2

    公开(公告)日：2015-04-28

    申请号：US13566130

    申请日：2012-08-03

    申请人： David W. Abraham ,  Michael C. Gaidis

    发明人： David W. Abraham ,  Michael C. Gaidis

    IPC分类号： G11B5/127 ,  H04R31/00 ,  G11C11/16

    CPC分类号： G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49021 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49048 ,  Y10T29/49052

    摘要： A method for fabricating a synthetic antiferromagnetic device, includes depositing a reference layer on a first tantalum layer and including depositing a first cobalt iron boron layer, depositing a second cobalt iron boron layer on the first cobalt iron boron layer, depositing a second Ta layer on the second cobalt iron boron layer, depositing a magnesium oxide spacer layer on the reference layer and depositing a cap layer on the magnesium oxide spacer layer.

    摘要翻译： 一种用于制造合成反铁磁性器件的方法，包括在第一钽层上沉积参考层，并且包括沉积第一钴铁硼层，在第一钴铁硼层上沉积第二钴铁硼层，在第一钴铁硼层上沉积第二Ta层 第二钴铁硼层，在参考层上沉积氧化镁间隔层并在氧化镁间隔层上沉积覆盖层。