公开(公告)号：US20170255502A1

公开(公告)日：2017-09-07

申请号：US15505674

申请日：2015-07-09

Applicant: SONY CORPORATION

Inventor： YASUSHI FUJINAMI ,  KENICHI NAKANISHI ,  TSUNENORI SHIIMOTO ,  TETSUYA YAMAMOTO ,  TATSUO SHINBASHI ,  HIDEAKI OKUBO ,  HARUHIKO TERADA ,  KEN ISHII ,  HIROYUKI IWAKI ,  MATATOSHI HONJO

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1048 ,  G06F12/16 ,  G11C11/16 ,  G11C13/00 ,  G11C29/00 ,  G11C29/44 ,  G11C2029/0407

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.