公开(公告)号：US20170185478A1

公开(公告)日：2017-06-29

申请号：US15325191

申请日：2015-06-23

Applicant: SONY CORPORATION

Inventor： LUI SAKAI ,  KEIICHI TSUTSUI ,  YASUSHI FUJINAMI ,  HIROYUKI IWAKI ,  KEN ISHII ,  NAOHIRO ADACHI ,  RYOJI IKEGAYA ,  KENICHI NAKANISHI

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/16 ,  G06F2212/1032 ,  G06F2212/7209 ,  G11C29/52 ,  G11C2029/0411

Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory.

公开(公告)号：US20190056884A1

公开(公告)日：2019-02-21

申请号：US15768597

申请日：2016-07-27

Applicant: SONY CORPORATION

Inventor： KEN ISHII ,  HIROYUKI IWAKI ,  KENICHI NAKANISHI ,  YASUSHI FUJINAMI ,  TATSUO SHINBASHI

IPC: G06F3/06

Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories.In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request.

公开(公告)号：US20170109099A1

公开(公告)日：2017-04-20

申请号：US15311555

申请日：2015-05-19

Applicant: SONY CORPORATION

Inventor： HIROYUKI IWAKI ,  KEN ISHII ,  RYOJI IKEGAYA ,  KENICHI NAKANISHI ,  YASUSHI FUJINAMI ,  NAOHIRO ADACHI

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/141 ,  G06F11/1666 ,  G06F11/20

Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful.

公开(公告)号：US20210376836A1

公开(公告)日：2021-12-02

申请号：US17250310

申请日：2019-07-05

Applicant: SONY CORPORATION

Inventor： AKITO SEKIYA ,  TOMOHIRO MATSUMOTO ,  HIROYUKI YAMAGISHI ,  YASUSHI FUJINAMI ,  YUSUKE OIKE ,  RYOJI IKEGAYA

IPC: H03K19/21 ,  G06F7/544 ,  G06F7/523 ,  G06F7/50

Abstract: A signal processing circuit (12) outputs, in a case where a first timing at which a first input signal changes is earlier than or same as a second timing at which a second input signal changes, a first output signal at the first timing and a second output signal at the second timing, and outputs, in a case where the first timing is later than the second timing, the first output signal and the second output signal at the second timing.

公开(公告)号：US20170322842A1

公开(公告)日：2017-11-09

申请号：US15529697

申请日：2015-10-08

Applicant: SONY CORPORATION

Inventor： HIROYUKI IWAKI ,  KEIICHI TSUTSUI ,  LUI SAKAI ,  KENICHI NAKANISHI ,  HIDEAKI OKUBO ,  YASUSHI FUJINAMI

IPC: G06F11/10 ,  G06F12/10 ,  H03M13/15

CPC classification number: G06F11/1048 ,  G06F12/10 ,  G06F12/16 ,  G06F2212/65 ,  G11C13/0035 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6325

Abstract: Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.

公开(公告)号：US20200310681A1

公开(公告)日：2020-10-01

申请号：US16311100

申请日：2017-04-17

Applicant: SONY CORPORATION

Inventor： KEN ISHII ,  HIROYUKI IWAKI ,  KENICHI NAKANISHI ,  YASUSHI FUJINAMI ,  TATSUO SHINBASHI

IPC: G06F3/06 ,  G06F11/10

Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.

公开(公告)号：US20170255502A1

公开(公告)日：2017-09-07

申请号：US15505674

申请日：2015-07-09

Applicant: SONY CORPORATION

Inventor： YASUSHI FUJINAMI ,  KENICHI NAKANISHI ,  TSUNENORI SHIIMOTO ,  TETSUYA YAMAMOTO ,  TATSUO SHINBASHI ,  HIDEAKI OKUBO ,  HARUHIKO TERADA ,  KEN ISHII ,  HIROYUKI IWAKI ,  MATATOSHI HONJO

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1048 ,  G06F12/16 ,  G11C11/16 ,  G11C13/00 ,  G11C29/00 ,  G11C29/44 ,  G11C2029/0407

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.