公开(公告)号：US20170329724A1

公开(公告)日：2017-11-16

申请号：US15527374

申请日：2015-10-08

Applicant: SONY CORPORATION

Inventor： HARUHIKO TERADA ,  LUI SAKAI ,  HIDEAKI OKUBO ,  KEIICHI TSUTSUI

IPC: G06F12/16 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F12/16 ,  G06F11/1441 ,  G06F11/22 ,  G11C11/5685 ,  G11C13/0023 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/028 ,  G11C2013/0054

Abstract: To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

公开(公告)号：US20170322842A1

公开(公告)日：2017-11-09

申请号：US15529697

申请日：2015-10-08

Applicant: SONY CORPORATION

Inventor： HIROYUKI IWAKI ,  KEIICHI TSUTSUI ,  LUI SAKAI ,  KENICHI NAKANISHI ,  HIDEAKI OKUBO ,  YASUSHI FUJINAMI

IPC: G06F11/10 ,  G06F12/10 ,  H03M13/15

CPC classification number: G06F11/1048 ,  G06F12/10 ,  G06F12/16 ,  G06F2212/65 ,  G11C13/0035 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/6325

Abstract: Reduction in deterioration of a memory cell in a non-volatile memory is achieved. A memory controller is configured to include a time measuring unit, an elapsed time determination unit, and a read unit. The time measuring unit measures time elapsed from predetermined timing on an address where data written. The elapsed time determination unit determines whether the elapsed time exceeds a fixed amount of time upon receiving an instruction to read out the data from the address. The read control unit causes reading-out of the data from the address to pause in a case where the elapsed time is determined not to exceed the fixed amount of time.

公开(公告)号：US20190095136A1

公开(公告)日：2019-03-28

申请号：US16086833

申请日：2016-12-28

Applicant: SONY CORPORATION

Inventor： HIDEAKI OKUBO ,  KENICHI NAKANISHI

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/18 ,  G06F13/24

Abstract: To perform both writing and reading at a high speed by utilizing a first memory and a second memory that has a lower writing speed and a higher reading speed than the first memory. A writing unit writes writing data related to a writing command in a first memory when the writing command is executed. A transfer unit transfers the writing data from the first memory to a second memory at a predetermined timing. A reading unit performs reading of reading data from the second memory with higher priority than from the first memory when a reading command is executed.

公开(公告)号：US20170255502A1

公开(公告)日：2017-09-07

申请号：US15505674

申请日：2015-07-09

Applicant: SONY CORPORATION

Inventor： YASUSHI FUJINAMI ,  KENICHI NAKANISHI ,  TSUNENORI SHIIMOTO ,  TETSUYA YAMAMOTO ,  TATSUO SHINBASHI ,  HIDEAKI OKUBO ,  HARUHIKO TERADA ,  KEN ISHII ,  HIROYUKI IWAKI ,  MATATOSHI HONJO

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/079 ,  G06F11/1048 ,  G06F12/16 ,  G11C11/16 ,  G11C13/00 ,  G11C29/00 ,  G11C29/44 ,  G11C2029/0407

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.