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    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS
    1.
    发明申请
    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS 有权
    存储单元结构，制造存储器的方法和存储器装置

    公开(公告)号：US20160260774A1

    公开(公告)日：2016-09-08

    申请号：US15029038

    申请日：2014-10-10

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Shunichi SUKEGAWA ,  Takashi YOKOYAMA ,  Masanori HOSOMI ,  Yutaka HIGO

    IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G11C11/16 ,  H01L27/1203 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    Abstract: A memory cell structure, a method of manufacturing a memory, and a memory apparatus that conform a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat are provided. A memory cell includes: a transistor with a first diffusion layer formed in a bottom portion of a concave portion, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first and second diffusion layers in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

    Abstract translation: 存储器单元结构，制造存储器的方法和符合MRAM的存储单元结构的存储器件，其降低了连接到MTJ的绘制布线的电阻，从而减小了存储单元的面积，并且避免了性能 提供了由于热引起的MTJ的降解。 存储单元包括：具有形成在凹部的底部的第一扩散层的晶体管，以及形成在所述凹部的两个相对侧壁部的上端部的第二扩散层，以在所述第一 和两个侧壁部分中的第二扩散层; 以及设置在第一扩散层下方的存储元件。 第一扩散层通过在硅衬底变薄之后形成的接触电连接到存储元件。

    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
    2.
    发明申请
    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS 有权

    公开(公告)号：US20210043676A1

    公开(公告)日：2021-02-11

    申请号：US17068783

    申请日：2020-10-12

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Keiji TATANI ,  Hajime INOUE ,  Ryuichi KANAMURA

    IPC: H01L27/146

    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS
    5.
    发明申请
    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS 审中-公开

    公开(公告)号：US20180226571A1

    公开(公告)日：2018-08-09

    申请号：US15947053

    申请日：2018-04-06

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Shunichi SUKEGAWA ,  Takashi YOKOYAMA ,  Masanori HOSOMI ,  Yutaka HIGO

    IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G11C11/16 ,  H01L27/1203 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat.A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS
    6.
    发明申请
    MEMORY CELL STRUCTURE, METHOD OF MANUFACTURING A MEMORY, AND MEMORY APPARATUS 审中-公开

    公开(公告)号：US20170141298A1

    公开(公告)日：2017-05-18

    申请号：US15417572

    申请日：2017-01-27

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Shunichi SUKEGAWA ,  Takashi YOKOYAMA ,  Masanori HOSOMI ,  Yutaka HIGO

    IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02

    CPC classification number: H01L43/08 ,  G11C11/16 ,  H01L27/1203 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat.A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
    7.
    发明申请
    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20200035744A1

    公开(公告)日：2020-01-30

    申请号：US16555067

    申请日：2019-08-29

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Keiji TATANI ,  Hajime INOUE ,  Ryuichi KANAMURA

    IPC: H01L27/146

    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
    8.
    发明申请
    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20190229145A1

    公开(公告)日：2019-07-25

    申请号：US16373105

    申请日：2019-04-02

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Keiji TATANI ,  Hajime INOUE ,  Ryuichi KANAMURA

    IPC: H01L27/146

    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
    9.
    发明申请
    SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS 审中-公开

    公开(公告)号：US20180350867A1

    公开(公告)日：2018-12-06

    申请号：US16042094

    申请日：2018-07-23

    Applicant: SONY CORPORATION

    Inventor： Taku UMEBAYASHI ,  Keiji TATANI ,  Hajime INOUE ,  Ryuichi KANAMURA

    IPC: H01L27/146

    Abstract: A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication.

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