PLAY MUTE CIRCUIT AND METHOD
    2.
    发明公开

    公开(公告)号:US20230378923A1

    公开(公告)日:2023-11-23

    申请号:US17747845

    申请日:2022-05-18

    CPC classification number: H03G3/3026 H03G3/348 H03G3/3036 H03K4/06

    Abstract: In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.

    Back-to-back power switch controller

    公开(公告)号:US10917086B2

    公开(公告)日:2021-02-09

    申请号:US16410857

    申请日:2019-05-13

    Abstract: In an embodiment, a power switch controller for driving a back-to-back power switch includes: an amplifier having a supply terminal configured to receive a supply voltage, an output configured to be coupled to a gate terminal of the back-to-back power switch, a first input configured to be coupled a source terminal of the back-to-back power switch, and a second input coupled to the output of the amplifier. The amplifier is configured to generate an output voltage at the output of the amplifier, the output voltage being an offset voltage higher than a voltage at the first input of the amplifier.

    Layout and pad floor plan of power transistor for good performance of SPU and STOG
    8.
    发明授权
    Layout and pad floor plan of power transistor for good performance of SPU and STOG 有权
    功率晶体管的布局和焊盘平面图,实现了SPU和STOG的良好性能

    公开(公告)号:US08691684B2

    公开(公告)日:2014-04-08

    申请号:US13906223

    申请日:2013-05-30

    CPC classification number: H01L21/4871 H01L23/4824 H01L2924/0002 H01L2924/00

    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

    Abstract translation: 布置用于音频应用的功率晶体管以最小化热点。 热点由不均匀的功耗或过度集中的电流密度产生。 源极和漏极焊盘相对于彼此设置以促进均匀的功率耗散。 在没有通孔的情况下,交叉金属指和上金属层直接连接到下金属层,以改善电流密度分布。 这种布局改进了17%的失败检测测试。

    LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG
    9.
    发明申请
    LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG 有权
    功率晶体管的布局和平铺布局,用于SPU和STOG的良好性能

    公开(公告)号:US20130267087A1

    公开(公告)日:2013-10-10

    申请号:US13906223

    申请日:2013-05-30

    CPC classification number: H01L21/4871 H01L23/4824 H01L2924/0002 H01L2924/00

    Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

    Abstract translation: 布置用于音频应用的功率晶体管以最小化热点。 热点由不均匀的功耗或过度集中的电流密度产生。 源极和漏极焊盘相对于彼此设置以促进均匀的功率耗散。 在没有通孔的情况下,交叉金属指和上金属层直接连接到下金属层,以改善电流密度分布。 这种布局改进了17%的失败检测测试。

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