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公开(公告)号：US20230400359A1
公开(公告)日：2023-12-14
申请号：US17836817
申请日：2022-06-09
发明人： Dino COSTANZO , Yan ZHANG , Guixi SUN
摘要： A three-phase load is powered by an SPWM driven inverter having a single shunt-topology. During operation, drain-to-source resistances of transistors of each branch of the inverter are determined. Interpolation is performed on assumed drain-to-source resistances of the transistors for different temperatures to produce a non-linear model of drain-to-source resistance to temperature for the transistors, and the drain-to-source resistances determined during operation and the non-linear model are used to estimate temperature values of the transistors. Driving of the inverter can be adjusted so that conductivity of each branch is set so that power delivered by that branch is as high as possible without exceeding an allowed drain current threshold representing a threshold junction temperature. In addition, driving of the inverter can be ceased if the temperature of a transistor exceeds the threshold temperature.
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公开(公告)号：US20230266845A1
公开(公告)日：2023-08-24
申请号：US17677119
申请日：2022-02-22
发明人： Bowei Chen , Yue Ding , Guodong Sun
CPC分类号： G06F3/0418 , G06F3/0446 , G06F3/0412 , G06F3/0447
摘要： A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.
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公开(公告)号：US20220214384A1
公开(公告)日：2022-07-07
申请号：US17378226
申请日：2021-07-16
发明人： Dino COSTANZO , Cheng Pan CAI , Xi Yu XU
IPC分类号： G01R19/25 , H02P27/08 , H02M1/00 , G01R15/14 , H02M7/5387
摘要： A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.
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公开(公告)号：US20220173706A1
公开(公告)日：2022-06-02
申请号：US17107269
申请日：2020-11-30
发明人： Hong Wu Lin , Giovanni Gonano , Edoardo Botti
IPC分类号： H03F3/217 , H03K17/687 , H04R3/00
摘要： In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.
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公开(公告)号：US20210203293A1
公开(公告)日：2021-07-01
申请号：US17200490
申请日：2021-03-12
发明人： Ru Feng Du , Qi Yu Liu
IPC分类号： H03G1/04 , H03K19/017 , H03F3/217 , H03K19/20 , H03K19/003 , H03G3/30 , H03K19/096
摘要： In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
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公开(公告)号：US10935592B2
公开(公告)日：2021-03-02
申请号：US16057089
申请日：2018-08-07
IPC分类号： G01R31/26 , H03K17/0814 , G05F3/08 , G01R19/00 , H03K17/687
摘要： A circuit includes a field effect transistor having a gate driven via a drive signal. The field effect transistor has a drain-source voltage drop indicative of the intensity of a current flowing in the current path through the field effect transistor. The circuit also includes a pair of sensing transistors that include a first sensing field effect transistor arranged with its drain and gate coupled with the drain and the gate of the field effect transistor, respectively, and a second sensing field effect transistor having a gate configured for receiving a replica of the drive signal. The second sensing field effect transistor is arranged with its current path in series with the current path of the first sensing field effect transistor. A sensing signal at a sensing node is indicative of the current intensity flowing in the current path of the field effect transistor.
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公开(公告)号：US20200287507A1
公开(公告)日：2020-09-10
申请号：US16291971
申请日：2019-03-04
发明人： Ru Feng Du , XiangSheng Li
摘要： In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.
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公开(公告)号：US10749515B1
公开(公告)日：2020-08-18
申请号：US16669154
申请日：2019-10-30
发明人： Hong Wu Lin
摘要： A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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公开(公告)号：US10719114B2
公开(公告)日：2020-07-21
申请号：US15966808
申请日：2018-04-30
发明人： Andy Lin , Johnny Yoon , Danny Sheng
摘要： An embodiment is a circuit for use with a display device, the circuit including: a first input node configured to be operatively coupled to a first port of a data source device that provides the display device with data, to receive a first direct voltage used for a real-time display of the data on the display device; and at least one output node, configured to operatively provide the display device with at least one output voltage generated based on the first direct voltage, wherein the first port is isolated from a data port used to transmit the data.
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公开(公告)号：US10122279B2
公开(公告)日：2018-11-06
申请号：US15592757
申请日：2017-05-11
发明人： Hai Bo Zhang , Jerry Huang
摘要： A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.
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