公开(公告)号：US20150221782A1

公开(公告)日：2015-08-06

申请号：US14607577

申请日：2015-01-28

Applicant: STMICROELECTRONICS (TOURS) SAS ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  UNIVERSITE FRANCOIS RABELAIS

Inventor： Arnaud YVON ,  Daniel ALQUIER ,  Yvon Cordier

IPC: H01L29/872 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/66212

Abstract: A Schottky diode may include a semiconductor substrate having first and second opposing surfaces, and a buffer layer over the first surface of the semiconductor substrate. The Schottky diode may include a first doped GaN layer over the buffer layer and having first and second opposing surfaces, the second surface of the first doped GaN layer being adjacent the buffer layer, and a second doped GaN layer over the second surface of the first doped GaN layer and having a dopant concentration level less than a dopant concentration level of the first doped GaN layer. The buffer layer, the first doped GaN layer, and the second doped GaN layer may define an opening. The Schottky diode may include a first metallization layer being coupled to the semiconductor substrate and to the first surface of the first doped GaN layer and being in the opening.

Abstract translation: 肖特基二极管可以包括具有第一和第二相对表面的半导体衬底和在半导体衬底的第一表面上的缓冲层。 肖特基二极管可以包括在缓冲层上的第一掺杂GaN层，并且具有第一和第二相对表面，第一掺杂GaN层的第二表面与缓冲层相邻，第二掺杂GaN层在第一 并且具有小于第一掺杂GaN层的掺杂剂浓度水平的掺杂剂浓度水平。 缓冲层，第一掺杂GaN层和第二掺杂GaN层可以限定开口。 肖特基二极管可以包括耦合到半导体衬底和第一掺杂GaN层的第一表面并处于开口中的第一金属化层。

公开(公告)号：US20220209024A1

公开(公告)日：2022-06-30

申请号：US17556634

申请日：2021-12-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Arnaud YVON ,  Lionel JAOUEN

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L21/761

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a first doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

公开(公告)号：US20240204112A1

公开(公告)日：2024-06-20

申请号：US18593490

申请日：2024-03-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Arnaud YVON ,  Lionel JAOUEN

IPC: H01L29/861 ,  H01L21/761 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/8611 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/66128 ,  H01L29/66136

Abstract: A device includes a diode. The anode of the diode includes first, second, and third areas. The first area partially covers the second area and has a forst doping level greater than a second doping level of the second area. The second area partially covers the third area and has the second doping level greater than a third doping level of the third area. A first insulating layer partially overlaps the first and second areas.

公开(公告)号：US20240021604A1

公开(公告)日：2024-01-18

申请号：US18478465

申请日：2023-09-29

Applicant: STMICROELECTRONICS APPLICATION GMBH ,  STMICROELECTRONICS (TOURS) SAS

Inventor： Mathieu ROUVIERE ,  Arnaud YVON ,  Mohamed SAADNA ,  Vladimir SCARPA

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/872

CPC classification number: H01L27/0629 ,  H01L21/0254 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

公开(公告)号：US20150064881A1

公开(公告)日：2015-03-05

申请号：US14464158

申请日：2014-08-20

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Arnaud YVON

IPC: H01L21/306 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/0661 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/30625 ,  H01L21/3228 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66212 ,  H01L29/872

Abstract: A method is for treating a doped gallium nitride substrate of a first conductivity type, having dislocations emerging on the side of at least one of its surfaces. The method may include: a) forming, where each dislocation emerges, a recess extending into the substrate from the at least one surface; and b) filling the recesses with doped gallium nitride of the second conductivity type.

Abstract translation: 一种用于处理第一导电类型的掺杂氮化镓衬底的方法，其具有出现在其表面的至少一个侧面上的位错。 该方法可以包括：a）在每个错位出现的地方形成从所述至少一个表面延伸到所述基底中的凹部; 以及b）用所述第二导电类型的掺杂氮化镓填充所述凹部。