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1.发明申请HIGH FREQUENCY LOW-GAIN NOISE RING-TYPE VCO OSCILLATOR LEADING TO A LOW-NOISE/AREA PLL 有权低噪声低噪声环型VCO振荡器引导到低噪声/区域PLL公开(公告)号：US20150145608A1
公开(公告)日：2015-05-28
申请号：US14090759
申请日：2013-11-26
Applicant: STMicroelectronics International N.V.
Inventor： Amit Katyal
IPC: H03K3/03
CPC classification number: H03K3/0315 , G05F3/262 , H03L7/0995
Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.
Abstract translation: 锁相环包括压控振荡器和向压控振荡器提供驱动电流的电流镜电路。 电流镜电路包括偏置电流发生器和电流镜晶体管之间的滤波器。 该滤波器包括以小占空比同时驱动的第一和第二开关。
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Patent Agency Ranking
2.发明授权公开(公告)号：US09018046B2
公开(公告)日：2015-04-28
申请号：US13841099
申请日：2013-03-15
Inventor： Joshipura Jwalant , Nitin Bansal , Amit Katyal , Massimiliano Picca
CPC classification number: H05K3/30 , G06F17/5063 , Y10T29/49002 , Y10T29/4913 , Y10T29/49169
Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
Abstract translation: 一种用于集成电压调节器的区域有效的分布式装置，其包括耦合在芯片的I / O轨上的一对PADS与至少一个具有所述装置的小尺寸部分的附加填充单元之间的填充单元耦合到所述I / O 用于在所述芯片的周围分配所述设备的部分的轨道。 该装置作为小尺寸部分耦合在所述第二填充单元的下部，用于将所述装置分布在所述芯片的外围并提供最大的面积利用率。
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公开(公告)号：US09337851B2
公开(公告)日：2016-05-10
申请号：US14734820
申请日：2015-06-09
Applicant: STMicroelectronics International N.V.
Inventor： Amit Katyal
Abstract: An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors.
Abstract translation: 描述了一种电子电路，其中基于电荷泵的数字锁相环电路增加了附加的电路以监视和控制噪声和功率消耗。 附加电路包括比较器和测量台，其被配置为测量和调整锁相环的单位增益带宽。 在一个实施例中，测量级包括两个频率 - 电流转换器和相关联的电流镜。
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4.发明申请公开(公告)号：US20150358025A1
公开(公告)日：2015-12-10
申请号：US14734820
申请日：2015-06-09
Applicant: STMicroelectronics International N.V.
Inventor： Amit Katyal
Abstract: An electronic circuit is described in which a charge pump-based digital phase locked loop circuit is augmented with additional circuitry to monitor and control noise and power consumption. The additional circuitry includes a comparator and a measurement stage configured to measure and adjust a unity gain bandwidth of the phase locked loop. In one embodiment, the measurement stage includes two frequency-to-current converters and associated current mirrors.
Abstract translation: 描述了一种电子电路，其中基于电荷泵的数字锁相环电路增加了附加的电路以监视和控制噪声和功率消耗。 附加电路包括比较器和测量台，其被配置为测量和调整锁相环的单位增益带宽。 在一个实施例中，测量级包括两个频率 - 电流转换器和相关联的电流镜。
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公开(公告)号：US20140132308A1
公开(公告)日：2014-05-15
申请号：US13674394
申请日：2012-11-12
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Amit Katyal
Abstract: A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.
Abstract translation: 锁相环（PLL）电路包含开关电容电路和反馈电路，以减少实现锁定状态的时间。 在第一模式中，使用压控振荡器（VCO）的频率来调节VCO的控制电压以实现粗略的锁定状态。 在第二模式中，使用参考频率来控制电荷泵以更精确地调整控制电压以实现PLL的精细锁定。 由于VCO频率明显高于参考频率，所以在第一模式期间，控制电压以更大的速率变化。 在一些实施例中，可以通过将VCO控制电压初始化为特定电压来进一步降低实现锁定的时间，以便在粗略地减小启动时的控制电压与第一模式开始时的控制电压之间的差异 锁。
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6.发明授权High frequency low-gain noise ring-type VCO oscillator leading to a low-noise/area PLL 有权高频低增益噪声环型VCO振荡器导致低噪声/区域PLL公开(公告)号：US09401699B2
公开(公告)日：2016-07-26
申请号：US14090759
申请日：2013-11-26
Applicant: STMicroelectronics International N.V.
Inventor： Amit Katyal
CPC classification number: H03K3/0315 , G05F3/262 , H03L7/0995
Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.
Abstract translation: 锁相环包括压控振荡器和向压控振荡器提供驱动电流的电流镜电路。 电流镜电路包括偏置电流发生器和电流镜晶体管之间的滤波器。 该滤波器包括以小占空比同时驱动的第一和第二开关。
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