PULSE WIDTH MODULATOR WITH REDUCED PULSE WIDTH

    公开(公告)号:US20230006679A1

    公开(公告)日:2023-01-05

    申请号:US17931043

    申请日:2022-09-09

    IPC分类号: H03L7/081 H03L7/085

    摘要: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

    PROGRAMMABLE-ON-THE-FLY FRACTIONAL DIVIDER IN ACCORDANCE WITH THIS DISCLOSURE

    公开(公告)号:US20210281254A1

    公开(公告)日:2021-09-09

    申请号:US17193532

    申请日:2021-03-05

    IPC分类号: H03K5/00 H03K19/20

    摘要: A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

    TRANSCONDUCTANCE BOOSTED CASCODE COMPENSATION FOR AMPLIFIER

    公开(公告)号:US20200343869A1

    公开(公告)日:2020-10-29

    申请号:US16829088

    申请日:2020-03-25

    摘要: A differential pair of transistors receives input voltages. Current mirror transistors and cascode transistors are coupled to the differential pair of transistors. The differential pair of transistors is coupled between the cascode transistors and a tail transistor that draws a first bias current from a tail node, the first bias current having a magnitude equal to a product of a total bias current and a constant that is less than one. A first current source transistor draws a second bias current from a node between the differential pair and cascode transistors so the second bias current bypasses one transistor of the differential pair of transistors. The second bias current has a magnitude equal to a product of the total bias current and a value equal to one minus the constant. An output stage is biased by an output at node between the cascode transistors and the current mirror transistors.

    DIGITAL RESISTOR HAVING LOW AREA AND IMPROVED LINEARITY

    公开(公告)号:US20230317323A1

    公开(公告)日:2023-10-05

    申请号:US18193387

    申请日:2023-03-30

    摘要: An electronic device having a digitally controlled resistor is provided. The digitally controlled resistor includes various switch-resistor segments between voltage nodes. In one embodiment, the switch-resistor segment may include a resistor and a switch coupled parallel to the resistor. In another embodiment, the switch-resistor segment may include a resistor, a complement switch coupled in series with the resistor, and a switch coupled parallel to the resistor and the complement switch. Each switch included in the switch-resistor segment operates based on digital bits. Based on the logic value (either ‘0’ or ‘1’) assigned, the switches turn ON (when logic value is ‘1’) and OFF (when logic value is ‘0’). In some embodiments, the switches and the resistor included in the switch-transistor segment are arranged in a symmetrical manner between voltage nodes.

    LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT
    5.
    发明公开

    公开(公告)号:US20230163769A1

    公开(公告)日:2023-05-25

    申请号:US17969251

    申请日:2022-10-19

    摘要: A phase lock loop (PLL) circuit includes a phase-frequency detector (PFD) circuit that determines a difference between a reference clock signal and a feedback clock signal to generate up/down control signals responsive to that difference. Charge pump and loop filter circuitry generates an integral signal component control signal and a proportional signal component control signal in response to the up/down control signals. The integral signal component control signal and proportional signal component control signal are separate control signals. A voltage controlled oscillator generates an oscillating output signal having a frequency controlled by the integral signal component control signal and the proportional signal component control signal. A divider circuit performs a frequency division on the oscillating output signal to generate the feedback clock signal.

    PULSE WIDTH MODULATOR WITH REDUCED PULSE WIDTH

    公开(公告)号:US20220166435A1

    公开(公告)日:2022-05-26

    申请号:US17525680

    申请日:2021-11-12

    IPC分类号: H03L7/081 H03L7/085

    摘要: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

    PROCESS COMPENSATED GAIN BOOSTING VOLTAGE REGULATOR

    公开(公告)号:US20200183439A1

    公开(公告)日:2020-06-11

    申请号:US16694028

    申请日:2019-11-25

    IPC分类号: G05F3/26 G05F1/575

    摘要: A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.