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公开(公告)号：US20170294234A1
公开(公告)日：2017-10-12
申请号：US15380919
申请日：2016-12-15
IPC分类号： G11C17/16 , H01L27/112 , H01L23/525
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/11206 , H01L28/00
摘要： An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.
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2.发明授权Embedded non-volatile memory with single polysilicon layer memory cells programmable through band-to-band tunneling-induced hot electron and erasable through fowler-nordheim tunneling 有权嵌入式非易失性存储器，单个多晶硅层存储单元，可通过带 - 带隧道诱导的热电子可编程，并可通过fowler-nordheim隧道进行擦除公开(公告)号：US09361982B2
公开(公告)日：2016-06-07
申请号：US14605350
申请日：2015-01-26
发明人： Luca Milani , Fabrizio Torricelli , Anna Richelli , Luigi Colalongo , Zsolt Miklos Kovàcs-Vajna
IPC分类号： G11C16/10 , G11C16/04 , G11C16/26 , H01L27/115 , H01L21/28 , H01L29/788 , H01L29/66
CPC分类号： G11C16/0408 , G11C16/10 , G11C16/26 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： A non-volatile memory includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cell includes a read portion and a control portion. The read portion and the control portion share an electrically floating layer of conductive material defining a first capacitive coupling with the read portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity greater than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current injects or extracts charge carriers into or from the electrically floating layer to store of a first logic value or a second logic value, respectively, in the memory cell.
摘要翻译： 非易失性存储器包括以多行和列排列的多个存储单元。 每个存储单元包括读取部分和控制部分。 读取部分和控制部分共享导电材料的电浮置层，其限定与读取部分的第一电容耦合和与控制部分的第二电容耦合。 第一电容耦合限定大于由第二电容耦合限定的第二容量的第一容量。 控制部分被配置为使得电流将电荷载流子注入或从电浮置层中提取，或者从电浮置层中提取电荷载体，以将第一逻辑值或第二逻辑值分别存储在存储单元中。
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公开(公告)号：US10468425B2
公开(公告)日：2019-11-05
申请号：US14605303
申请日：2015-01-26
发明人： Luca Milani , Fabrizio Torricelli , Anna Richelli , Luigi Colalongo , Zsolt Miklos Kovàcs-Vajna
IPC分类号： H01L27/115 , H01L27/11521 , H01L27/11519 , H01L27/1156 , H01L29/66 , H01L29/788 , H01L27/11558
摘要： A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an electrically floating layer of conductive material defining a first capacitive coupling with the access portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity lower than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current extracts charge carriers from the electrically floating layer through Fowler-Nordheim tunneling to store a first logic value in the memory cell. The access portion is configured so that an electric current injects charge carriers in the electrically floating layer by injection of band-to-band tunneling-induced hot electrons to store a second logic value, respectively, in the memory cell.
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公开(公告)号：US09922722B2
公开(公告)日：2018-03-20
申请号：US15380919
申请日：2016-12-15
IPC分类号： G11C7/00 , G11C17/16 , H01L23/525 , H01L27/112
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/11206 , H01L28/00
摘要： An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.
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5.发明授权Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling 有权嵌入式非易失性存储器，单个多晶硅层存储单元可通过通道热电子编程，并可通过fowler-nordheim隧道进行擦除公开(公告)号：US09368209B2
公开(公告)日：2016-06-14
申请号：US14605246
申请日：2015-01-26
发明人： Luca Milani , Fabrizio Torricelli , Anna Richelli , Luigi Colalongo , Zsolt Miklos Kovàcs-Vajna
IPC分类号： G11C16/10 , G11C16/04 , H01L27/115 , H01L21/28 , H01L29/66 , H01L29/788
CPC分类号： G11C16/0408 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.
摘要翻译： 非易失性存储器包括以行和列排列的存储单元。 每个存储器单元包括程序/读取部分和擦除部分，其共享限定与程序/读取部分的第一电容耦合的导电材料的电浮置层和与擦除部分的第二电容耦合。 第一电容耦合限定大于由第二电容耦合限定的第二电容的第一电容。 擦除部分被配置为使得电流从电浮动层提取电荷载流子以将第一逻辑值存储在存储器单元中。 程序/读取部分被进一步配置成使得电流注入电浮置层中的电荷载流子以将第二逻辑值存储在存储单元中。
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