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公开(公告)号：US11152430B2
公开(公告)日：2021-10-19
申请号：US16375571
申请日：2019-04-04
Inventor： Philippe Boivin , Jean Jacques Fagot , Emmanuel Petitprez , Emeline Souchier , Olivier Weber
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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公开(公告)号：US20170117178A1
公开(公告)日：2017-04-27
申请号：US15401896
申请日：2017-01-09
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Petitprez
IPC: H01L21/768 , H01L29/06 , H01L23/532 , H01L29/45 , H01L23/535 , H01L29/78 , H01L29/08
CPC classification number: H01L21/76832 , H01L21/0217 , H01L21/283 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76816 , H01L21/76835 , H01L21/76895 , H01L21/823475 , H01L21/84 , H01L23/485 , H01L23/53295 , H01L23/535 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/41733 , H01L29/42364 , H01L29/45 , H01L29/518 , H01L29/7838
Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
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公开(公告)号：US11818901B2
公开(公告)日：2023-11-14
申请号：US17489425
申请日：2021-09-29
Inventor： Philippe Boivin , Jean Jacques Fagot , Emmanuel Petitprez , Emeline Souchier , Olivier Weber
IPC: H01L21/8222 , H10B63/00 , H10N70/20 , H10N70/00
CPC classification number: H10B63/32 , H10N70/231 , H10N70/826
Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.
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Patent Agency Ranking
公开(公告)号：US09608080B2
公开(公告)日：2017-03-28
申请号：US14639232
申请日：2015-03-05
Inventor： Ahmet S. Ozcan , Emmanuel Petitprez
IPC: H01L29/417 , H01L29/16 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/78 , H01L29/66
CPC classification number: H01L29/41783 , H01L29/0649 , H01L29/16 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/6653 , H01L29/66628 , H01L29/7838
Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.
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公开(公告)号：US09922871B2
公开(公告)日：2018-03-20
申请号：US15401896
申请日：2017-01-09
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Petitprez
IPC: H01L21/768 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/45 , H01L23/535 , H01L23/532
CPC classification number: H01L21/76832 , H01L21/0217 , H01L21/283 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76816 , H01L21/76835 , H01L21/76895 , H01L21/823475 , H01L21/84 , H01L23/485 , H01L23/53295 , H01L23/535 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/41733 , H01L29/42364 , H01L29/45 , H01L29/518 , H01L29/7838
Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerge onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
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6.发明授权Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit 有权在例如在SOI衬底上特别是FDSOI衬底上制造的集成电路的有源区上产生接触的工艺以及相应的集成电路公开(公告)号：US09590064B2
公开(公告)日：2017-03-07
申请号：US14962976
申请日：2015-12-08
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Petitprez
IPC: H01L21/8234 , H01L29/423 , H01L21/768 , H01L29/51 , H01L21/02 , H01L21/84 , H01L29/06 , H01L21/283
CPC classification number: H01L21/76832 , H01L21/0217 , H01L21/283 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76816 , H01L21/76835 , H01L21/76895 , H01L21/823475 , H01L21/84 , H01L23/485 , H01L23/53295 , H01L23/535 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/41733 , H01L29/42364 , H01L29/45 , H01L29/518 , H01L29/7838
Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provided and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
Abstract translation: 集成电路包括位于半导体衬底上方的有源区。 空腔与有源区域相邻并且在绝缘区域中延伸到半导体区域附近。 提供绝缘多层，并且导电接触件在绝缘层内延伸出来，以露出到活性区域并进入空腔。 绝缘多层包括覆盖接触外部的有源区并衬在空腔的壁上的第一绝缘层。 附加的绝缘层覆盖衬在空腔壁上的第一绝缘层的部分。 触点到达腔中的附加绝缘层。 绝缘区域位于第一绝缘层的顶部和由接触件周围的绝缘材料制成的附加绝缘层。
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7.发明申请PROCESS FOR PRODUCING A CONTACT ON AN ACTIVE ZONE OF AN INTEGRATED CIRCUIT, FOR EXAMPLE PRODUCED ON AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT 有权用于在集成电路的活动区域上生产接触的方法，例如在SOI衬底上生产的示例，特别是FDSOI衬底和相应的集成电路公开(公告)号：US20160372562A1
公开(公告)日：2016-12-22
申请号：US14962976
申请日：2015-12-08
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Emmanuel Petitprez
IPC: H01L29/423 , H01L21/768 , H01L21/283 , H01L21/02 , H01L21/84 , H01L29/06 , H01L21/8234 , H01L29/51
CPC classification number: H01L21/76832 , H01L21/0217 , H01L21/283 , H01L21/76801 , H01L21/76802 , H01L21/76805 , H01L21/76816 , H01L21/76835 , H01L21/76895 , H01L21/823475 , H01L21/84 , H01L23/485 , H01L23/53295 , H01L23/535 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/41733 , H01L29/42364 , H01L29/45 , H01L29/518 , H01L29/7838
Abstract: An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far as into the vicinity of a semiconductor region. An insulating multilayer is provide and an electrically conductive contact extends within the insulating multilayer to emerging onto the active zone and into the cavity. The insulating multilayer includes a first insulating layer covering the active zone outside the contact and lining the walls of the cavity. An additional insulating layer covers the portion of the first insulating layer lining the walls of the cavity. The contact reaches the additional insulating layer in the cavity. An insulating region lies on top of the first insulating layer and the additional insulating layer made from insulating material around the contact.
Abstract translation: 集成电路包括位于半导体衬底上方的有源区。 空腔与有源区域相邻并且在绝缘区域中延伸到半导体区域附近。 提供绝缘多层，并且导电接触件在绝缘多层中延伸出现到有源区域并进入空腔。 绝缘多层包括覆盖接触外部的有源区并衬在空腔的壁上的第一绝缘层。 附加的绝缘层覆盖衬在空腔壁上的第一绝缘层的部分。 触点到达腔中的附加绝缘层。 绝缘区域位于第一绝缘层的顶部和由接触件周围的绝缘材料制成的附加绝缘层。
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8.发明申请METHOD AND STRUCTURE TO REDUCE PARASITIC CAPACITANCE IN RAISED SOURCE/DRAIN SILICON-ON-INSULATOR DEVICES 有权降低源/绝缘硅绝缘体器件中的PARASIIC电容的方法和结构公开(公告)号：US20160260811A1
公开(公告)日：2016-09-08
申请号：US14639232
申请日：2015-03-05
Inventor： Ahmet S. Ozcan , Emmanuel Petitprez
IPC: H01L29/417 , H01L29/06 , H01L29/66 , H01L29/51 , H01L29/78 , H01L29/16 , H01L29/423
CPC classification number: H01L29/41783 , H01L29/0649 , H01L29/16 , H01L29/42364 , H01L29/51 , H01L29/518 , H01L29/665 , H01L29/6653 , H01L29/66628 , H01L29/7838
Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.
Abstract translation: 本发明的一个方面涉及一种绝缘体上硅器件，其包括在衬底上的绝缘层上的硅层; 硅层上的凸起源和升高的漏极; 升高源和升高的漏极之间的门; 将所述栅极与所述凸起源分离并且基本上覆盖所述栅极的第一侧壁的第一间隔件; 第二间隔件，其将所述栅极与所述升高的漏极分隔开并且基本上覆盖所述栅极的第二侧壁; 以及在升高的源极上的低k层，所述升高的漏极，所述栅极以及所述第一间隔物和所述第二间隔物中的每一个; 以及在低k层上的介电层。
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