公开(公告)号：US20140340133A1

公开(公告)日：2014-11-20

申请号：US14276567

申请日：2014-05-13

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics Pvt. Ltd.

发明人： Gilles Gasiot ,  Sylvain Clerc ,  Junaid Yousuf ,  Maximilien Glorieux

IPC分类号： H03K19/003 ,  H03L7/08

CPC分类号： H03K19/0033 ,  G11C5/005 ,  H03K3/0375 ,  H03K3/356121 ,  H03L7/08 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/095 ,  H03L7/18

摘要： A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

摘要翻译： 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。

公开(公告)号：US08837206B2

公开(公告)日：2014-09-16

申请号：US13669226

申请日：2012-11-05

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC分类号： G11C11/00

CPC分类号： G11C19/28

摘要： A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

摘要翻译： 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。

公开(公告)号：US20130121070A1

公开(公告)日：2013-05-16

申请号：US13669226

申请日：2012-11-05

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC分类号： G11C11/40

CPC分类号： G11C19/28

摘要： A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

摘要翻译： 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。